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STANDARD PRODUCT
PM4351 COMET
DATA SHEET
PMC-1970624
ISSUE 10
COMBINED E1/T1 TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL
377
5. If FULL=0, the TDPR FIFO has room for at least 1 more byte to be written.
Write the data into the TDPR Transmit Data register. Go to step 6.
6. If more data bytes are to be transmitted in the packet, go to step 2.
7. If all bytes in the packet have been sent, set the EOM bit in the TDPR
Configuration register to logic 1. Go to step 1.
Figure 37
- Typical Data Frame
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
0
FLAG
Address (high)
(low)
CONTROL
Frame Check
Sequence
0
1
1
1
1
1
1
0
FLAG
data bytes written to the
Transmit Data Register
and serially transmitted,
bit 1 first
BIT:
appended after EOM
is set, if CRC is set
14.3 Using the Internal HDLC Receivers
On power up of the system, the RDLC should be disabled by setting the EN bit in
the Configuration Register to logic 0. The Interrupt Control Register should then
be initialized to enable the INTB output and to select the FIFO buffer fill level at
which an interrupt will be generated. If the INTE bit is not set to logic 1, the
Status Register must be continuously polled to check the interrupt status (INTR)
bit.
After the Interrupt Control Register has been written, the RDLC can be enabled
at any time by setting the EN bit in the Configuration Register to logic 1. When
the RDLC is enabled, it will assume the link status is idle (all ones) and
immediately begin searching for flags. When the first flag is found, an interrupt
will be generated, and a dummy byte will be written into the FIFO buffer. This is
done to provide alignment of link up status with the data read from the FIFO.