![](http://datasheet.mmic.net.cn/330000/PM4351_datasheet_16444271/PM4351_446.png)
STANDARD PRODUCT
PM4351 COMET
DATA SHEET
PMC-1970624
ISSUE 10
COMBINED E1/T1 TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL
422
The indirect read programming sequence for the TPSC (RPSC) is as follows:
1. Check that the BUSY bit in the TPSC (RPSC) μP Access Status Register is
logic 0.
2. Write RWB=1 and the channel address to the TPSC (RPSC) Channel Indirect
Address/Control Register.
3. Poll the BUSY bit, waiting until it goes to a logic 0. The BUSY bit will go to
logic 1 immediately after step 2 and remain at logic 1 until the request is
complete.
4. Read the requested channel data from the TPSC (RPSC) Channel Indirect
Data Buffer register.
5. If there is more data to be read, go back to step 1.
14.10 Isolating an Interrupt
When the INTB pin goes low, the following procedure may be used to isolate the
interrupt source.
1. Read the Interrupt Source Registers (Registers 007H, 008H and 009H). The
bit corresponding to any block with an outstanding interrupt will be set to logic
1 in these registers.
2. Read the register(s) containing the interrupt status bits of the interrupting
block in order to determine the event causing the interrupt. A typical block
interrupt has two related bits: an enable bit (EVENTE for instance) and an
interrupt status bit (EVENTI for instance). EVENTI will go to logic 1 when the
triggering event occurs, and goes low when the register containing it is read;
the setting of EVENTE has no effect on the value of EVENTI. However, a
chip interrupt will only be caused if EVENTE is logic 1 and EVENTI is logic 1.
Thus, both the interrupt status bit(s) and their respective enables may need to
be read in order to determine which event caused an interrupt. Specific
interrupt setups may differ from this model, however.
14.11 Using the Performance Monitor Counter Values
All PMON event counters are of sufficient length so that the probability of counter
saturation over a one second interval is very small (less than 0.001%). The odds
of any one of the counters saturating during a one second sampling interval go
up as the bit error rate (BER) increases. At some point, the probability of counter
saturation reaches 50%. This point varies, depending upon the framing format
and the type of event being counted. The BER at which the probability of