STANDARD PRODUCT
PM4351 COMET
DATA SHEET
PMC-1970624
ISSUE 10
COMBINED E1/T1 TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL
363
Figure 29
- Receive Backplane at 2.048 Mbit/s (T1 Mode)
6
0
2
3
4
5
1
7
7
F
C
A
B
D
D
6
4
5
0
1
2
3
C
A
B
D
7
0
BRPCM
BRSIG
BRFP
2.048 M(CMS = 0)
4.096 MHz BRCLK
(CMS = 1)
X
X
X
X
X
Time Slot 31
(used)
Time Slot 0
(unused)
Time Slot 1
(used)
A 2.048 Mbit/s backplane in T1 mode is configured by setting the RATE[1:0] bits
of the Receive Backplane Configuration register to 'b01 and the E1/T1B bit of
the Global Configuration register to a logic 0. In Figure 29, BRFP, BRPCM and
BRSIG are configured to be updated on the falling edge of BRCLK by setting the
FE and DE bits of the Receive Backplane Configuration register to logic 0. Once
the RATE[1:0] bits are set, a reset is required to change to a new RATE[1:0].
In Figure 29, the MAP register bit is logic 0. As shown, every fourth time slot is
unused, starting with the first. If MAP is a logic 1, time slots 0 through 23 would
be used. The framing bit is presented during bit 0 of time slot 0, so that only bits
1 to 7 of time slot 0 are ignored. The TSOFF[6:0], BOFF_EN and BOFF[2:0]
register bits are all logic zero; therefore, BRFP is expected to be aligned to the
first bit of the frame.
Figure 30
- Receive Backplane at 2.048 Mbit/s (E1 Mode)
6
0
2
3
4
5
1
7
7
6
4
5
7
0
1
2
3
C
A
B
D
D
6
4
5
0
1
2
3
C
A
B
D
7
0
Time Slot 0
Time Slot 1
BRPCM
BRSIG
BRFP
Time Slot 31
X
X
X
2.048 MHz BRCLK
(CMS = 0)
4.096 M(CMS = 1)
A 2.048 Mbit/s backplane in E1 mode is configured by setting the RATE[1:0] bits
of the Receive Backplane Configuration register to 'b01 and E1/T1B bit of the
Global Configuration register to logic 1. In Figure 30, BRFP, BRPCM and BRSIG
are configured to be updated on the falling edge of BRCLK by setting the FE and
DE bits of the Receive Backplane Configuration register to logic 0. The
TSOFF[6:0], BOFF_EN and BOFF[2:0] register bits are all logic zero; therefore,