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STANDARD PRODUCT
PM4351 COMET
DATA SHEET
PMC-1970624
ISSUE 10
COMBINED E1/T1 TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL
189
Table 37
- SIGX Per-Channel T1 Data Conditioning
RINV[1]
SIGNINV
Effect on PCM Channel Data
0
1
0
0
0
1
PCM Channel data is unchanged
All 8 bits of the received PCM channel data are inverted
Only the MSB of the received PCM channel data is
inverted (SIGN bit inversion)
All bits EXCEPT the MSB of the received PCM channel
data is inverted (Magnitude inversion)
1
1
In E1 mode, the RINV[1:0] bits select bits within the timeslot are inverted.
The bit mapping is as shown in Table 38.
Table 38
- SIGX Per-Channel E1 Data Conditioning
RINV[1]
RINV[0]
Effect on PCM Channel Data
0
0
1
1
0
1
0
1
do not invert
invert even bits (2,4,6,8)
invert odd bits (1,3,5,7)
invert all bits
Because of the distinct requirements for E1 and T1, the register bits have
different definitions in the two modes. In E1 mode bit 2 is defined as RINV[0];
whereas in T1 it is RFIX. RINV[1] has a different effect for the two modes.
In T1 mode, RFIX controls whether the signaling bit (the least significant bit of
the DS0 channel on BRPCM during signaling frames) is fixed to the polarity
specified by the RPOL bit. A logic 1 in the RFIX position enables bit fixing; a
logic 0 in the RFIX position disables bit fixing. Note that the RPSC functions
(inversion, digital milliwatt code insertion, trunk conditioning, and PRBS
detection or insertion) take place after bit fixing.
RPOL:
In T1 mode, the RPOL bit selects the logic level the signaling bit is fixed to
when bit fixing is enabled. When RPOL is a logic 1, the signaling is fixed to
logic 1. When RPOL is a logic 0, the signaling is fixed to logic 0.
RDEBE:
The RDEBE bit enables debouncing of timeslot/channel signaling bits. A
logic 1 in this bit position enables signaling debouncing while a logic 0