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参数资料
型号： S29WS064N0PBAW011
厂商： Spansion Inc.
英文描述： 256/128/64 MEGABIT CMOS 1.8 VOLT ONLY SIMULTANEOUS READ/WRITE BURST MODE FLASH MEMORY
中文描述： 256/128/64兆位的CMOS 1.8伏只有同时读/写突发模式闪存
文件页数： 16/99页
文件大小： 1091K
代理商： S29WS064N0PBAW011
January 25, 2005 S29WS-N_00_G0
21
Ad vance
Information
Data is output on A/DQ15-A/DQ0 pins after the access time (tOE) has elapsed from the falling
edge of OE#.
7.3
Synchronous (Burst) Read Mode &
Configuration Register
When a series of adjacent addresses needs to be read from the device (in order from lowest to
highest address), the synchronous (or burst read) mode can be used to significantly reduce the
overall time needed for the device to output array data. After an initial access time required for
the data from the first address location, subsequent data is output synchronized to a clock input
provided by the system.
The device offers both continuous and linear methods of burst read operation, which are dis-
cussed in subsections 7.3.3 and 7.3.4, and 7.3.5.
Since the device defaults to asynchronous read mode after power-up or a hardware reset, the
configuration register must be set to enable the burst read mode. Other Configuration Register
settings include the number of wait states to insert before the initial word (tIACC) of each burst
access, the burst mode in which to operate, and when RDY indicates data is ready to be read.
Prior to entering the burst mode, the system should first determine the configuration register set-
tings (and read the current register settings if desired via the Read Configuration Register
command sequence), and then write the configuration register command sequence. See Section
7.3.6, Configuration Register, and Table 12.1, Memory Array Commands for further details.
Figure 7.1. Synchronous/Asynchronous State Diagram
The device outputs the initial word subject to the following operational conditions:
tIACC specification: the time from the rising edge of the first clock cycle after addresses
are latched to valid data on the device outputs.
configuration register setting CR13–CR11: the total number of clock cycles (wait states)
that occur before valid data appears on the device outputs. The effect is that tIACC is
lengthened.
Power-up/
Hardware Reset
Asynchronous Read
Mode Only
Synchronous Read
Mode Only
Set Burst Mode
Configuration Register
Command for
Synchronous Mode
(CR15 = 0)
Set Burst Mode
Configuration Register
Command for
Asynchronous Mode
(CR15 = 1)
相关PDF资料
PDF描述
S29WS128N0LBFI111 256/128/64 MEGABIT CMOS 1.8 VOLT ONLY SIMULTANEOUS READ/WRITE BURST MODE FLASH MEMORY
S29WS128N0LBFI112 256/128/64 MEGABIT CMOS 1.8 VOLT ONLY SIMULTANEOUS READ/WRITE BURST MODE FLASH MEMORY
S29WS128N0LBFI113 256/128/64 MEGABIT CMOS 1.8 VOLT ONLY SIMULTANEOUS READ/WRITE BURST MODE FLASH MEMORY
S29WS128N0LBFW011 Test Clip; Current Rating:100A; Body Material:Steel; Features:Unmarked; Jaw Opening Max:1.625"; Overall Length:6" RoHS Compliant: NA
S29WS128N0LBFI011 256/128/64 MEGABIT CMOS 1.8 VOLT ONLY SIMULTANEOUS READ/WRITE BURST MODE FLASH MEMORY
相关代理商/技术参数
参数描述
S29WS064N0PBAW012 制造商:SPANSION 制造商全称:SPANSION 功能描述:256/128/64 Megabit (16/8/4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
S29WS064N0PBAW013 制造商:SPANSION 制造商全称:SPANSION 功能描述:256/128/64 MEGABIT CMOS 1.8 VOLT ONLY SIMULTANEOUS READ/WRITE BURST MODE FLASH MEMORY
S29WS064N0PBAW110 制造商:SPANSION 制造商全称:SPANSION 功能描述:256/128/64 MEGABIT CMOS 1.8 VOLT ONLY SIMULTANEOUS READ/WRITE BURST MODE FLASH MEMORY
S29WS064N0PBAW111 制造商:SPANSION 制造商全称:SPANSION 功能描述:256/128/64 MEGABIT CMOS 1.8 VOLT ONLY SIMULTANEOUS READ/WRITE BURST MODE FLASH MEMORY
S29WS064N0PBAW112 制造商:SPANSION 制造商全称:SPANSION 功能描述:256/128/64 MEGABIT CMOS 1.8 VOLT ONLY SIMULTANEOUS READ/WRITE BURST MODE FLASH MEMORY
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