S29WS064N0PBAW011 PDF资料下载(17/99 页)256/128/64 MEGABIT CMOS 1.8 VOLT ONLY SIMULTANEOUS READ/WRIT

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参数资料

型号：	S29WS064N0PBAW011
厂商：	Spansion Inc.
英文描述：	256/128/64 MEGABIT CMOS 1.8 VOLT ONLY SIMULTANEOUS READ/WRITE BURST MODE FLASH MEMORY
中文描述：	256/128/64兆位的CMOS 1.8伏只有同时读/写突发模式闪存
文件页数：	17/99页
文件大小：	1091K
代理商：	S29WS064N0PBAW011

S29WS-N_00_G0 January 25, 2005

Adva nce

Information

The device outputs subsequent words tBACC after the active edge of each successive clock cycle,

which also increments the internal address counter. The device outputs burst data at this rate sub-

ject to the following operational conditions:

starting address: whether the address is divisible by four (where A[1:0] is 00). A divisi-

ble-by-four address incurs the least number of additional wait states that occur after the

initial word. The number of additional wait states required increases for burst operations

in which the starting address is one, two, or three locations above the divisible-by-four

address (i.e., where A[1:0] is 01, 10, or 11).

boundary crossing: There is a boundary at every 128 words due to the internal architec-

ture of the device. One additional wait state must be inserted when crossing this boundary

if the memory bus is operating at a high clock frequency. Please refer to the tables below.

clock frequency: the speed at which the device is expected to burst data. Higher speeds

require additional wait states after the initial word for proper operation.

In all cases, with or without latency, the RDY output indicates when the next data is available to

be read.

Tables 7.2 -7.6 reflect wait states required for S29WS256/128/064N devices. Refer to the “Con-

figuration Register” table (CR11 - CR14) and timing diagrams for more details.

Table 7.2. Address Latency (S29WS256N)

Table 7.3. Address Latency (S29WS128N/S29WS064N)

Table 7.4. Address/Boundary Crossing Latency (S29WS256N @ 80/66 MHz)

Table 7.5. Address/Boundary Crossing Latency (S29WS256N @ 54MHz)

Word

Wait States

Cycle

x ws

1 ws

x ws

1 ws

x ws

1 ws

Word

Wait States

Cycle

5, 6, 7 ws

1 ws

5, 6, 7 ws

1 ws

5, 6, 7 ws

1 ws

Word

Wait States

Cycle

7, 6 ws

1 ws

7, 6 ws

1 ws

7, 6 ws

1 ws

7, 6 ws

1 ws

Word

Wait States

Cycle

5 ws

1 ws

5 ws

1 ws

5 ws

1 ws

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