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参数资料
| 型号： | SFCF8192H4BK4SA-I-QT-553-SMA |
| 厂商： | Swissbit NA Inc |
| 文件页数： | 18/99页 |
| 文件大小： | 0K |
| 描述： | FLASH SLC UDMA/MDMA/PIO 8G |
| 视频文件： | Swissbit Manufacturing Overview |
| RoHS指令信息： | Environment Protection Declaration |
| 标准包装： | 20 |
| 系列： | C-300 |
| 存储容量： | 8GB |
| 存储器类型： | CompactFlash? |
| 其它名称： | 1052-1012 |
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Signal Name
Dir.
Pin
Description
The CompactFlash Storage Card is Reset when the
RESET pin is high with the following important exception:
The host may leave the RESET pin open or keep it continually
high from the application of power without causing a
RESET
(PC Card Memory Mode)
continuous
Reset of the card. Under either of these conditions, the card
RESET
(PC Card I/O Mode)
– RESET
(True IDE Mode)
Vcc
(PC Card Memory Mode)
Vcc
(PC Card I/O Mode)
Vcc
(True IDE Mode)
– VS1, – VS2
(PC Card Memory Mode)
I
41
13, 38
shall emerge from power-up having completed an initial Reset.
The CompactFlash Storage Card is also Reset
when the Soft Reset bit in the Card Configuration Option
Register is set.
This signal is the same as the PC Card Memory Mode signal.
In the True IDE Mode, this input pin is the active low hardware
reset from the host.
+5V, +3.3V power.
Same for all modes.
Same for all modes.
Voltage Sense Signals. – VS1 is grounded on the Card and
sensed by the Host so that the CompactFlash Storage Card
CIS can be read at 3.3 volts and – VS2 is reserved by
PCMCIA for a secondary voltage and is not connected on the
– VS1, – VS2
(PC Card I/O Mode)
– VS1, – VS2
(True IDE Mode)
– WAIT
(PC Card Memory Mode)
– WAIT
(PC Card I/O Mode)
IORDY
(True IDE Mode – Except
Ultra DMA Mode)
-DDMARDY
(True IDE Mode – Ultra
DMA Write Mode)
O
O
33, 40
42
Card.
This signal is the same for all modes.
This signal is the same for all modes.
The – WAIT signal is driven low by the CompactFlash Storage
Card to signal the host to delay completion of a
memory or I/O cycle that is in progress.
This signal is the same as the PC Card Memory Mode signal.
In True IDE Mode, except in Ultra DMA modes, this output
signal may be used as IORDY.
In True IDE Mode, when Ultra DMA mode DMA Write is active,
this signal is asserted by the host to indicate that the device is
read to receive Ultra DMA data-in bursts. The device may
negate – DDMARDY to pause an Ultra DMA transfer.
In True IDE Mode, when Ultra DMA mode DMA Write is active,
DSTROBE
(True IDE Mode – Ultra
DMA Read Mode)
– WE
(PC Card Memory Mode)
this signal is the data out strobe generated by the device. Both
the rising and falling edge of DSTROBE cause data to be latched
by the host. The device may stop generating DSTROBE edges
to pause an Ultra DMA data-out burst.
This is a signal driven by the host and used for strobing memory
write data to the registers of the CompactFlash Storage
when the card is configured in the memory interface
– WE
(PC Card I/O Mode)
– WE
(True IDE Mode)
I
36
mode. It is also used for writing the configuration registers.
In PC Card I/O Mode, this signal is used for writing the
configuration registers.
In True IDE Mode, this input signal is not used and should be
connected to VCC by the host.
Memory Mode – The CompactFlash Storage Card
WP
(PC Card Memory Mode)
does not have a write protect switch. This signal is held low
after
the completion of the reset initialization sequence.
I/O Operation – When the CompactFlash Storage Card
– IOIS16
(PC Card I/O Mode)
O
24
is configured for I/O Operation Pin 24 is used for the – I/O
Selected is 16 Bit Port (-IOIS16) function. A Low signal indicates
that a 16 bit or odd byte only operation can be performed at the
addressed port.
– IOCS16
(True IDE Mode)
In True IDE Mode this output signal is asserted low when this
device is expecting a word data transfer cycle.
Swissbit AG
Industriestrasse 4
Swissbit reserves the right to change products or specifications without notice.
Revision: 1.51
CH-9552 Bronschhofen
Switzerland
www.swissbit.com
industrial@swissbit.com
C-300_data_sheet_CF-HxBK_Rev151.doc
Page 18 of 99
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