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参数资料
| 型号： | SFCF8192H4BK4SA-I-QT-553-SMA |
| 厂商： | Swissbit NA Inc |
| 文件页数： | 30/99页 |
| 文件大小： | 0K |
| 描述： | FLASH SLC UDMA/MDMA/PIO 8G |
| 视频文件： | Swissbit Manufacturing Overview |
| RoHS指令信息： | Environment Protection Declaration |
| 标准包装： | 20 |
| 系列： | C-300 |
| 存储容量： | 8GB |
| 存储器类型： | CompactFlash? |
| 其它名称： | 1052-1012 |
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6.5.4 Ultra DMA Phases of Operation
An Ultra DMA data transfer is accomplished through a series of Ultra DMA data-in or data-out bursts. Each Ultra
DMA burst has three mandatory phases of operation: the initiation phase, the data transfer phase, and the Ultra
DMA burst termination phase. In addition, an Ultra DMA burst may be paused during the data transfer phase (see:
6.5.4.4 , for the detailed protocol descriptions for each of these phases. Table 26: Ultra DMA Data Burst Timing
Requirements and Table 27: Ultra DMA Data Burst Timing Descriptions define the specific timing requirements). In
the following rules – DMARDY is used in cases that could apply to either – DDMARDY or – HDMARDY, and STROBE is
used in cases that could apply to either DSTROBE or HSTROBE. The following are general Ultra DMA rules.
1.
2.
An Ultra DMA burst is defined as the period from an assertion of – DMACK by the host to the subsequent
negation of – DMACK.
When operating in Ultra DMA modes 2, 1, or 0 a recipient shall be prepared to receive up to two data
words whenever an Ultra DMA burst is paused. When operating in Ultra DMA modes 6, 5, 4, or 3 a
recipient shall be prepared to receive up to three data words whenever an Ultra DMA burst is paused.
6.5.4.1 Ultra DMA Burst Initiation Phase Rules
1.
2.
3.
4.
5.
6.
7.
An Ultra DMA burst initiation phase begins with the assertion of DMARQ by a device and ends when the
sender generates a STROBE edge to transfer the first data word.
An Ultra DMA burst shall always be requested by a device asserting DMARQ.
When ready to initiate the requested Ultra DMA burst, the host shall respond by asserting – DMACK.
A host shall never assert – DMACK without first detecting that DMARQ is asserted.
For Ultra DMA data-in bursts: a device may begin driving D[15:00] after detecting that – DMACK is asserted,
STOP negated, and – HDMARDY is asserted.
After asserting DMARQ or asserting – DDMARDY for an Ultra DMA data-out burst, a device shall not negate
either signal until the first STROBE edge is generated.
After negating STOP or asserting – HDMARDY for an Ultra DMA data-in burst, a host shall not change the
state of either signal until the first STROBE edge is generated.
6.5.4.2 Ultra DMA Data transfer phase rules
1.
2.
The data transfer phase is in effect from after Ultra DMA burst initiation until Ultra DMA burst termination.
A recipient pauses an Ultra DMA burst by negating – DMARDY and resumes an Ultra DMA burst by
reasserting – DMARDY.
3. A sender pauses an Ultra DMA burst by not generating STROBE edges and resumes by generating STROBE
edges.
4. A recipient shall not signal a termination request immediately when the sender stops generating STROBE
edges. In the absence of a termination from the sender the recipient shall always negate – DMARDY and
wait the required period before signaling a termination request.
5. A sender may generate STROBE edges at greater than the minimum period specified by the enabled Ultra
DMA mode. The sender shall not generate STROBE edges at less than the minimum period specified by the
enabled Ultra DMA mode. A recipient shall be able to receive data at the minimum period specified by the
enabled Ultra DMA mode.
6.5.4.3 Ultra DMA Burst Termination Phase Rules
1.
2.
3.
4.
5.
6.
7.
8.
9.
Either a sender or a recipient may terminate an Ultra DMA burst.
Ultra DMA burst termination is not the same as command completion. If an Ultra DMA burst termination
occurs before command completion, the command shall be completed by initiation of a new Ultra DMA
burst at some later time or aborted by the host issuing a hardware or software reset or DEVICE RESET
command if implemented by the device.
An Ultra DMA burst shall be paused before a recipient requests a termination.
A host requests a termination by asserting STOP. A device acknowledges a termination request by
negating DMARQ.
A device requests a termination by negating DMARQ. A host acknowledges a termination request by
asserting STOP.
Once a sender requests a termination, the sender shall not change the state of STROBE until the recipient
acknowledges the request. Then, if STROBE is not in the asserted state, the sender shall return STROBE to
the asserted state. No data shall be transferred on this transition of STROBE.
A sender shall return STROBE to the asserted state whenever the sender detects a termination request
from the recipient. No data shall be transferred nor CRC calculated on this edge of DSTROBE.
Once a recipient requests a termination, the responder shall not change DMARDY from the negated state
for the remainder of an Ultra DMA burst.
A recipient shall ignore a STROBE edge when DMARQ is negated or STOP is asserted.
Swissbit AG
Industriestrasse 4
Swissbit reserves the right to change products or specifications without notice.
Revision: 1.51
CH-9552 Bronschhofen
Switzerland
www.swissbit.com
industrial@swissbit.com
C-300_data_sheet_CF-HxBK_Rev151.doc
Page 30 of 99
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