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参数资料
| 型号： | SFCF8192H4BK4SA-I-QT-553-SMA |
| 厂商： | Swissbit NA Inc |
| 文件页数： | 56/99页 |
| 文件大小： | 0K |
| 描述： | FLASH SLC UDMA/MDMA/PIO 8G |
| 视频文件： | Swissbit Manufacturing Overview |
| RoHS指令信息： | Environment Protection Declaration |
| 标准包装： | 20 |
| 系列： | C-300 |
| 存储容量： | 8GB |
| 存储器类型： | CompactFlash? |
| 其它名称： | 1052-1012 |
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LBA7-LBA0: Sector Number Register D7 to D0
LBA15-LBA8: Cylinder Low Register D7 to D0
LBA23-LBA16: Cylinder High Register D7 to D0
LBA27-LBA24: Drive/Head Register bits HS3 to HS0
9.8.3 Bit 5
This bit is set to ‘1’.
9.8.4 Bit 4 (DRV)
DRV is the drive number. When DRV is ‘0’, drive/card 0 is selected (Master). When DRV is ‘1’, drive/card 1 is selected
(Slave). The Card is set to Card 0 or 1 using the copy field (Drive #) of the PCMCIA Socket & Copy configuration
register.
9.8.5 Bit 3 (HS3)
When operating in the Cylinder, Head, Sector mode, this is bit 3 of the head number. It is bit 27 in the Logical
Block Address mode.
9.8.6 Bit 2 (HS2)
When operating in the Cylinder, Head, Sector mode, this is bit 2 of the head number. It is bit 26 in the Logical
Block Address mode.
9.8.7 Bit 1 (HS1)
When operating in the Cylinder, Head, Sector mode, this is bit 1 of the head number. It is Bit 25 in the Logical
Block Address mode.
9.8.8 Bit 0 (HS0)
When operating in the Cylinder, Head, Sector mode, this is bit 0 of the head number. It is Bit 24 in the Logical
Block Address mode.
Table 51: Drive/Head Register
D7
1
D6
LBA
D5
1
D4
DRV
D3
HS3
D2
HS2
D1
HS1
D0
HS0
9.9 Status & Alternate Status Registers
The Status & Alternate Status registers are located at addresses 1F7h [177h] and 3F6h [376h], respectively. Offsets
are 7h and Eh.
These registers return the Card status when read by the host.
Reading the Status Register clears a pending interrupt. Reading the Auxiliary Status Register does not clear a
pending interrupt.
The Status Register should be accessed in Byte mode; in Word mode it is recommended that Alternate Status
Register is used. The status bits are described as follows
9.9.1 Bit 7 (BUSY)
The busy bit is set when only the Card can access the command register and buffer, The host is denied access. No
other bits in this register are valid when this bit is set to ‘1’.
9.9.2 Bit 6 (RDY)
This bit indicates whether the device is capable of performing CompactFlash Memory Card operations. This bit is
cleared at power up and remains cleared until the Card is ready to accept a command.
9.9.3 Bit 5 (DWF)
When set this bit indicates a Write Fault has occurred.
9.9.4 Bit 4 (DSC)
This bit is set when the Card is ready.
Swissbit AG
Industriestrasse 4
Swissbit reserves the right to change products or specifications without notice.
Revision: 1.51
CH-9552 Bronschhofen
Switzerland
www.swissbit.com
industrial@swissbit.com
C-300_data_sheet_CF-HxBK_Rev151.doc
Page 56 of 99
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