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参数资料
| 型号： | SFCF8192H4BK4SA-I-QT-553-SMA |
| 厂商： | Swissbit NA Inc |
| 文件页数： | 37/99页 |
| 文件大小： | 0K |
| 描述： | FLASH SLC UDMA/MDMA/PIO 8G |
| 视频文件： | Swissbit Manufacturing Overview |
| RoHS指令信息： | Environment Protection Declaration |
| 标准包装： | 20 |
| 系列： | C-300 |
| 存储容量： | 8GB |
| 存储器类型： | CompactFlash? |
| 其它名称： | 1052-1012 |
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Figure 13: Ultra DMA Data-In Burst Device Termination Timing
Notes: The definitions for the STOP, HDMARDY, and DSTROBE signal lines are no longer in effect after DMARQ and
DMACK are negated.
6.5.4.4.5 Host Terminating an Ultra DMA Data-In Burst
The host terminates an Ultra DMA Data-In burst by following the steps lettered below. The timing
diagram is shown in Figure 14: Ultra DMA Data-In Burst Host Termination Timing. The timing
parameters are specified in Table 26: Ultra DMA Data Burst Timing Requirements and are
The following steps shall occur in the order they are listed unless otherwise specifically allowed:
a) The host shall not initiate Ultra DMA burst termination until at least one data word of an Ultra DMA burst
has been transferred.
b) The host shall initiate Ultra DMA burst termination by negating – HDMARDY. The host shall continue to
negate – HDMARDY until the Ultra DMA burst is terminated.
c) The device shall stop generating DSTROBE edges within t RFS of the host negating – HDMARDY
d) If the host negates – HDMARDY within t SR after the device has generated a DSTROBE edge, then the host
shall be prepared to receive zero or one additional data words. If the host negates HDMARDYgreater than
t SR after the device has generated a DSTROBE edge, then the host shall be prepared to receive zero, one or
two additional data words. The additional data words are a result of cable round trip delay and t RFS
timing for the device.
e) The host shall assert STOP no sooner than t RP after negating – HDMARDY. The host shall not negate STOP
again until after the Ultra DMA burst is terminated.
f)
The device shall negate DMARQ within t LI after the host has asserted STOP. The device shall not assert
DMARQ again until after the Ultra DMA burst is terminated.
g) If DSTROBE is negated, the device shall assert DSTROBE within t LI after the host has asserted STOP. No data
shall be transferred during this assertion. The host shall ignore this transition on DSTROBE. DSTROBE shall
remain asserted until the Ultra DMA burst is terminated.
h) The device shall release D[15:00] no later than t AZ after negating DMARQ.
i) The host shall drive DD D[15:00] no sooner than t ZAH after the device has negated DMARQ. For this step, the
host may first drive D[15:00] with the result of its CRC calculation (see 6.5.4.5 ).
Swissbit AG
Industriestrasse 4
Swissbit reserves the right to change products or specifications without notice.
Revision: 1.51
CH-9552 Bronschhofen
Switzerland
www.swissbit.com
industrial@swissbit.com
C-300_data_sheet_CF-HxBK_Rev151.doc
Page 37 of 99
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