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参数资料
| 型号： | SFCF8192H4BK4SA-I-QT-553-SMA |
| 厂商： | Swissbit NA Inc |
| 文件页数： | 47/99页 |
| 文件大小： | 0K |
| 描述： | FLASH SLC UDMA/MDMA/PIO 8G |
| 视频文件： | Swissbit Manufacturing Overview |
| RoHS指令信息： | Environment Protection Declaration |
| 标准包装： | 20 |
| 系列： | C-300 |
| 存储容量： | 8GB |
| 存储器类型： | CompactFlash? |
| 其它名称： | 1052-1012 |
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This bit is set to ‘0’ at power -up and taking the Card through a hardware reset.
7.1.2 LevlREQ
This bit is set to one (1) when Level Mode Interrupt is selected, and zero (0) when Pulse Mode is selected. Set to
zero (0) after Power Up.
7.1.3 Conf5 – Conf0 (Configuration Index)
These bits are used to select the operation mode of the Card as shown in Table 34 . This bit is set to ‘0’ after Power
Up.
Table 33: Configuration Option Register (default value: 00h)
Operation
R/W
D7
SRESET
D6
LevlREQ
D5
Conf5
D4
Conf4
D3
Conf3
D2
Conf2
D1
Conf1
D0
Conf0
Table 34: CompactFlash Memory Card Configurations
Conf5
0
0
0
0
Conf4
0
0
0
0
Conf3
0
0
0
0
Conf2
0
0
0
0
Conf1
0
0
1
1
Conf0
0
1
0
1
Mapping Mode
Memory
Contiguous I/O
Primary I/O
Secondary I/O
Card
Mode
Memory
I/O
I/O
I/O
Task File Register Address
0h – Fh, 400h – 7FFh
xx0h – xxFh
1F0h – 1F7h, 3F6h – 3F7h
170h – 177h, 376h – 377h
7.2 CompactFlash Memory Card Configurations
The Card Configuration and Status Register contains information about the Card’s status (see Table 35).
7.2.1 Changed
Indicates that one or both of the Pin Replacement register (CRDY, or CWProt) bits are set to ‘1’. When the Changed
bit is set, - STSCHG (Pin 46) is held Low and if the SigChg bit is ‘1’ the Card is configured for the I/O interface.
7.2.2 SigChg
This bit is set and reset by the host to enable and disable a state-change signal from the Status Register (issued
on Status Changed pin 46). If no state change signal is desired, this bit should be set ‘0’ and pin 46 ( -STSCHG) will
be held High while the Card is configured for I/O.
7.2.3 Iois8
The host sets this bit to ‘1’ if the Card is to be configured in 8 bit I/O Mode. The Card is always configured for both
8 and 16 bit I/O, so this bit is ignored.
7.2.4 PwrDwn
This bit indicates whether the Card is in the power saving mode or active mode. When the PwrDwn bit is set to ‘1’,
the Card enters power down mode. When set to ‘0’, the Card enters active mode. The READY value on Pin
Replacement Register becomes BUSY when this bit is changed. READY will not become Ready until the power state
requested has been entered. The Card automatically powers down when it is idle and powers back up when it
receives a command.
7.2.5 Int
This bit represents the internal state of the interrupt request. It is available whether or not the I/O interface has
been configured. It remains valid until the condition which caused the interrupt request has been serviced. If
interrupts are disabled by the – IEN bit in the Device Control Register, this bit is ‘0’.
Table 35: Card Configuration an d Status Register (default value: 00h)
Operation
Read
Write
D7
Changed
0
D6
SigChg
SigChg
D5
IOIS8
IOIS8
D4
0
0
D3
0
0
D2
PwrDwn
PwrDwn
D1
Int
0
D0
0
0
7.3 Pin Replacement Register (204h in Attribute Memory)
This register contains information on the state of the READY signal when configured in memory mode and the
Swissbit AG
Industriestrasse 4
Swissbit reserves the right to change products or specifications without notice.
Revision: 1.51
CH-9552 Bronschhofen
Switzerland
www.swissbit.com
industrial@swissbit.com
C-300_data_sheet_CF-HxBK_Rev151.doc
Page 47 of 99
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