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参数资料
| 型号： | SFCF8192H4BK4SA-I-QT-553-SMA |
| 厂商： | Swissbit NA Inc |
| 文件页数： | 40/99页 |
| 文件大小： | 0K |
| 描述： | FLASH SLC UDMA/MDMA/PIO 8G |
| 视频文件： | Swissbit Manufacturing Overview |
| RoHS指令信息： | Environment Protection Declaration |
| 标准包装： | 20 |
| 系列： | C-300 |
| 存储容量： | 8GB |
| 存储器类型： | CompactFlash? |
| 其它名称： | 1052-1012 |
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b) The host shall generate an HSTROBE edge to latch the new word no sooner than t DVS after changing the
state of D[15:00]. The host shall generate an HSTROBE edge no more frequently than t CYC for the selected
Ultra DMA mode. The host shall not generate two rising or falling HSTROBE edges more frequently than 2t cyc
for the selected Ultra DMA mode.
c)
The host shall not change the state of D[15:00] until at least t DVH after generating an HSTROBE edge to latch
the data.
d) The host shall repeat steps (a), (b), and (c) until the data transfer is complete or an Ultra DMA burst is
paused, whichever occurs first.
Figure 16: Sustained Ultra DMA Data-Out Burst Timing
Note: Data (D15:D00) and HSTROBE signals are shown at both the device and the host to emphasize that cable
settling time as well as cable propagation delay shall not allow the data signals to be considered stable at the
device until some time after they are driven by the host.
6.5.4.4.8 Device Pausing an Ultra DMA Data-Out Burst
The device pauses an Ultra DMA Data-Out burst by following the steps lettered below. The
timing diagram is shown in Figure 17: Ultra DMA Data-Out Burst Device Pause Timing. The
timing parameters are specified in Table 26: Ultra DMA Data Burst Timing Requirements and are
The following steps shall occur in the order they are listed unless otherwise specifically allowed:
a) The device shall not pause an Ultra DMA burst until at least one data word of an Ultra DMA burst has been
transferred.
b) The device shall pause an Ultra DMA burst by negating – DDMARDY.
c) The host shall stop generating HSTROBE edges within t RFS of the device negating – DDMARDY.
d) If the device negates – DDMARDY within t SR after the host has generated an HSTROBE edge, then the device
shall be prepared to receive zero or one additional data words. If the device negates – DDMARDY greater
than t SR after the host has generated an HSTROBE edge, then the device shall be prepared to receive zero,
one or two additional data words. The additional data words are a result of cable round trip delay and t RFS
timing for the host.
e) The device shall resume an Ultra DMA burst by asserting – DDMARDY.
Swissbit AG
Industriestrasse 4
Swissbit reserves the right to change products or specifications without notice.
Revision: 1.51
CH-9552 Bronschhofen
Switzerland
www.swissbit.com
industrial@swissbit.com
C-300_data_sheet_CF-HxBK_Rev151.doc
Page 40 of 99
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