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| 型号： | SFCF8192H4BK4SA-I-QT-553-SMA |
| 厂商： | Swissbit NA Inc |
| 文件页数： | 54/99页 |
| 文件大小： | 0K |
| 描述： | FLASH SLC UDMA/MDMA/PIO 8G |
| 视频文件： | Swissbit Manufacturing Overview |
| RoHS指令信息： | Environment Protection Declaration |
| 标准包装： | 20 |
| 系列： | C-300 |
| 存储容量： | 8GB |
| 存储器类型： | CompactFlash? |
| 其它名称： | 1052-1012 |
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9. CF-ATA Registers
The following section describes the hardware registers used by the host software to issue commands to the Card.
These registers are collectively referred to as the ‘task file’.
In accordance with the PCMCIA specification, each register that is located at an odd offset address can be accessed
in the PC Card Memory or PC Card I/O modes. The register can be addressed in two ways:
Using the normal register address.
Using the corresponding even address (normal address -1) when – CE1 is High and – CE2 Low, unless – IOIS16
is High (not asserted by the card) and an I/O cycle is in progress. Register data are input or output on data
bus lines D15-D8.
In True IDE mode, the size of the transfer is based solely on the register being addressed. All registers are 8-bit
only except for the Data Register, which is normally 16 bits. However, they can be configured to be accessed in 8-
bit mode for non-DMA operations, by using a Set Features command (see Section 10.20 ).
9.1 Data Register
The Data register is located at address 1F0h [170h], offset 0h, 8h, and 9h.
The Data Register is a 16 bit register used to transfer data blocks between the Card data buffer and the Host. This
register overlaps the Error Register. Table 48 and Table 49 describe the combinations of Data register access and
explain the overlapped Data and Error/Feature Registers. Because of the overlapped registers, access to the 1F1h,
171h or offset 1 are not defined for Word (-CE2 and –CE1 set to ‘0’) operations, and are treated as accesses to the
Word Data Register. The duplicated registers at offsets 8, 9 and Dh have no restrictions on the operations that can
be performed.
Table 48: Data Register Access (Memory and I/O mode)
-REG
Data Register
Word Data Register
Even Data Register
Odd Data Register
Odd Data Register
Error/Feature Register
Error/Feature Register
Error/Feature Register
-CE2
0
1
1
0
1
0
0
-CE1
0
0
0
1
0
1
0
A0
X
0
1
X
1
X
X
-
-
-
-
-
-
-
(1)
Offset
0h, 8h, 9h
0h, 8h
9h
8h, 9h
1h, Dh
1h
Dh
Data Bus
D15 to D0
D7 to D0
D7 to D0
D15 to D8
D7 to D0
D15 to D8
D15 to D8
22
– REG signal is mode dependent. It must be Low when the Card operates in I/O Mode and High when it operates in
Memory Mode.
Table 49: Data Register Access (True IDE mode)
Data Register
PIO Word Data Register
DMA Word Data Register
PIO Byte Data Register (Selected Using Set
-CS1
1
1
1
-CS0
0
1
0
A0
0
X
0
-DMACK
1
0
1
Offset
0h
X
0h
Data Bus
D15 to D0
D15 to D0
D7 to D0
Features Command)
9.2 Error Register
The Error register is a read-only register, located at address 1F1h [171h], offset 1h, 0Dh.
This read only register contains additional information about the source of an error when an error is indicated in
bit 0 of the Status register. The bits are defined in Table 50 This register is accessed on data bits D15 to D8 during
a write operation to offset 0 with – CE2 Low and – CE1 High.
9.2.1 Bit 7 (BBK)
This bit is set when a Bad Block is detected.
9.2.2 Bit 6 (UNC)
This bit is set when an Uncorrectable Error is encountered.
9.2.3 Bit 5
This bit is ‘0’.
9.2.4 Bit 4 (IDNF)
This bit is set if the requested sector ID is in error or cannot be found.
Swissbit AG
Industriestrasse 4
Swissbit reserves the right to change products or specifications without notice.
Revision: 1.51
CH-9552 Bronschhofen
Switzerland
www.swissbit.com
industrial@swissbit.com
C-300_data_sheet_CF-HxBK_Rev151.doc
Page 54 of 99
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