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参数资料
| 型号： | SFCF8192H4BK4SA-I-QT-553-SMA |
| 厂商： | Swissbit NA Inc |
| 文件页数： | 41/99页 |
| 文件大小： | 0K |
| 描述： | FLASH SLC UDMA/MDMA/PIO 8G |
| 视频文件： | Swissbit Manufacturing Overview |
| RoHS指令信息： | Environment Protection Declaration |
| 标准包装： | 20 |
| 系列： | C-300 |
| 存储容量： | 8GB |
| 存储器类型： | CompactFlash? |
| 其它名称： | 1052-1012 |
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Figure 17: Ultra DMA Data-Out Burst Device Pause Timing
Notes:
1.
2.
The device may negate DMARQ to request termination of the Ultra DMA burst no sooner than tRP after
-DDMARDY is negated.
After negating – DDMARDY, the device may receive zero, one, two, or three more data words from the host.
6.5.4.4.9 Device Terminating an Ultra DMA Data-Out Burst
The device terminates an Ultra DMA Data-Out burst by following the steps lettered below. The timing diagram for
the operation is shown in Figure 18: Ultra DMA Data-Out Burst Device Termination Timing. The timing parameters
are specified in Table 26: Ultra DMA Data Burst Timing Requirements and are described in Table 27: Ultra DMA Data
The following steps shall occur in the order they are listed unless otherwise specifically allowed:
a) The device shall not initiate Ultra DMA burst termination until at least one data word of an Ultra DMA
burst has been transferred.
b) The device shall initiate Ultra DMA burst termination by negating – DDMARDY.
c) The host shall stop generating an HSTROBE edges within t RFS of the device negating – DDMARDY.
d) If the device negates – DDMARDY within t SR after the host has generated an HSTROBE edge, then the device
shall be prepared to receive zero or one additional data words. If the device negates – DDMARDY greater
than t SR after the host has generated anHSTROBE edge, then the device shall be prepared to receive zero,
one or two additional data words. The additional data words are a result of cable round trip delay and
tRFS timing for the host.
e) The device shall negate DMARQ no sooner than t RP after negating – DDMARDY. The device shall not assert
DMARQ again until after the Ultra DMA burst is terminated.
f)
The host shall assert STOP within t LI after the device has negated DMARQ. The host shall not negate STOP
again until after the Ultra DMA burst is terminated.
g) If HSTROBE is negated, the host shall assert HSTROBE within tLI after the device has negated DMARQ. No
data shall be transferred during this assertion. The device shall ignore this transition of HSTROBE. HSTROBE
shall remain asserted until the Ultra DMA burst is terminated.
h) The host shall place the result of its CRC calculation on D[15:00] (see 6.5.4.5 ).
i)
j)
The host shall negate – DMACK no sooner than t MLI after the host has asserted HSTROBE and STOP and the
device has negated DMARQ and – DDMARDY, and no sooner than t DVS after placing the result of its CRC
calculation on D[15:00].
The device shall latch the host’s CRC data from D[15:00] on the negating edge of – DMACK.
k) The device shall compare the CRC data received from the host with the results of its own CRC calculation. If
a miscompare error occurs during one or more Ultra DMA bursts for any one command.
Swissbit AG
Industriestrasse 4
Swissbit reserves the right to change products or specifications without notice.
Revision: 1.51
CH-9552 Bronschhofen
Switzerland
www.swissbit.com
industrial@swissbit.com
C-300_data_sheet_CF-HxBK_Rev151.doc
Page 41 of 99
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