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| 型号： | SFCF8192H4BK4SA-I-QT-553-SMA |
| 厂商： | Swissbit NA Inc |
| 文件页数： | 51/99页 |
| 文件大小： | 0K |
| 描述： | FLASH SLC UDMA/MDMA/PIO 8G |
| 视频文件： | Swissbit Manufacturing Overview |
| RoHS指令信息： | Environment Protection Declaration |
| 标准包装： | 20 |
| 系列： | C-300 |
| 存储容量： | 8GB |
| 存储器类型： | CompactFlash? |
| 其它名称： | 1052-1012 |
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8. Software interface
8.1 CF-ATA Drive Register Set Definition and Protocol
The CompactFlash Memory Card can be configured as a high performance I/O device through:
Standard PC-AT disk I/O address spaces
o
o
1F0h-1F7h, 3F6h-3F7h (primary);
170h-177h, 376h-377h (secondary) with IRQ 14 (or other available IRQ).
Any system decoded 16 Byte I/O block using any available IRQ.
Memory space.
Communication to or from the Card is done using the Task File registers which provide all the necessary registers
for control and status information. The PCMCIA interface connects peripherals to the host using four-register
mapping methods. Table 43: I/O Configurations is a detailed description of these methods:
Table 43: I/O Configurations
Standards Configurations
Config Index
0
1
2
3
I/O or Memory
Memory
I/O
I/O
I/O
Address
0h-Fh, 400h-7FFh
xx0h-xxFh
1F0-1F7h, 3F6h-3F7h
170-177h, 376h-377h
Description
Memory Mapped
I/O Mapped 16 Continuous Registers
Primary I/O Mapped
Secondary I/O Mapped
8.2 Memory Mapped Addressing
When the Card registers are accessed via memory references, the registers appear in the common memory space
window: 0-2Kbytes as shown in Table 44: Memory Mapped Decoding . This window accesses the Data Register
FIFO. It does not allow random access to the data buffer within the Card.
Register 0 is accessed with – CE1 and – CE2 Low, as a Word register on the combined Odd and Even Data Bus (D15 to
D0). It can also be accessed with – CE1 Low and – CE2 High, by a pair of Byte accesses to offset 0. The address space
of this Word register overlaps the address space of the Error and Feature Byte-wide registers at offset 1. When
accessed twice as Byte register with – CE1 Low, the first Byte is the even Byte of the Word and the second is the
odd Byte. A Byte access to address 0 with – CE1 High and – CE2 Low accesses the Error (read) or Feature (write)
register.
Registers at offset 8, 9 and D are non-overlapping duplicates of the registers at offset 0 and 1. Register 8 is
equivalent to register 0, while register 9 accesses the odd Byte. Therefore, if the registers are Byte accessed in the
order 9 then 8 the data will be transferred odd Byte then even Byte. Repeated Byte accesses to register 8 or 0 will
access consecutive (even then odd) Bytes from the data buffer. Repeated Word accesses to register 8, 9 or 0 will
access consecutive Words from the data buffer, however repeated Byte accesses to register 9 are not supported.
Repeated alternating Byte accesses to registers 8 then 9 will access consecutive (even then odd) Bytes from the
data buffer.
Accesses to even addresses between 400h and 7FFh access register 8. Accesses to odd addresses between 400h
and 7FFh access register 9. This 1 kByte memory window to the data register is provided so that hosts can perform
memory-to-memory block moves to the data register when the register lies in memory space. Some hosts, such
as the X86 processors, must increment both the source and destination addresses when executing the memory-
to-memory block move instruction. Some PCMCIA socket adapters also have embedded auto incrementing address
logic.
A Word access to address at offset 8 will provide even data on the least significant Byte of the data bus, along
with odd data at offset 9 on the most significant Byte of the data bus.
Swissbit AG
Industriestrasse 4
Swissbit reserves the right to change products or specifications without notice.
Revision: 1.51
CH-9552 Bronschhofen
Switzerland
www.swissbit.com
industrial@swissbit.com
C-300_data_sheet_CF-HxBK_Rev151.doc
Page 51 of 99
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