- 您现在的位置：买卖IC网 > PDF目录98080 > SII3114CT176 PCI BUS CONTROLLER, PQFP176 PDF资料下载
参数资料
| 型号： | SII3114CT176 |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP176 |
| 封装： | TQFP-176 |
| 文件页数： | 104/127页 |
| 文件大小： | 564K |
| 代理商： | SII3114CT176 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页当前第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页
SiI3114 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
SiI-DS-0103-D
70
2007 Silicon Image, Inc.
Serial ATA SActive
Address Offset: 10CH / 18CH / 30CH / 38CH
Access Type: Read/Write 1/Clear
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
SActive bits
The bits of this register may be written with a 1, but are cleared if the corresponding bits of the second dword of a
FIS are set when the SDevice Bits FIS is received. All 32 bits may be cleared by writing 0x0000_0000 to the
register; individual bits may not be cleared except by the hardware.
SMisc
Address Offset: 140H / 1C0H / 340H / 3C0H
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
FIS_Done
Transmit
_FIS
Transmit
_OK
IFIS_OK
Int
rlckFIS
R
e
ject
_IF
Accept_IF
R
x_IFIS
S
DB
pterr
Scr_dis
Cont_dis
VS_Lock_Abort
fpdmawr
dmainen
dmaouten
Transmit
_B
IST
devdrvn
nienf
is_dis
srst
C
o
mW
ake
pm_f
iscf
g
pm_locken
re
ffi
s
m
ode
P
M
CHG
P
MMO
DE
Reserved
PM
R
E
Q
This register contains bits for controlling Serial ATA power management, ComWake, loopback modes, and FIS
transfers.
Bit [31]: FIS_Done (R/W) – This bit is used to indicate to the link logic that all the data for the Transparent
FIS has been transferred and that the link can proceed to close out the FIS. This is used in Transparent
FIS transmission. Please refer to the “FIS Support” section on page 85 for more details.
Bit [30]: Transmit_FIS (W)– This bit is used to signal the link logic to start the process of transmitting a
Transparent FIS. Please refer to the “FIS Support” section on page 85 for more details.
Bit [29]: Transmit_OK (R)– This bit is used in Transparent FIS transmission. It is used by the link to signal
to the host that the current Transparent FIS has been successfully transferred to the device, and that R_OK
has been received.
Bit [28]: IFIS_OK (R)– This bit is used in the reception of Interlocked FISes. This bit is set by the link logic
to inform the host that the current Interlocked FIS has been successfully received with no errors.
Bit [27]: IntrlckFIS (R)– This bit is set to indicate to the host driver that the link has detected an the arrival
of an interlocked FIS and that the host should set up the DMA engine to start transfer of data
Bit [26]: Reject_IFIS (W)– This bit is set by the host driver to indicate to the link that the current Interlocked
FIS should be rejected. The link logic will respond to the device with an R_ERR when the complete FIS has
been received.
Bit [25]: Accept_IFIS (W)– This bit is set by the host driver to indicate to the link that the current interlocked
FIS should be accepted. The link logic will respond to the device with R_OK
Bit [24]: Rx_IFIS (W)– This bit is set by the host driver to inform the link/transport logic that the host has
set up the DMA engine to transfer the incoming Interlocked FIS and that the DMA cycles can begin
Bit [23]: SDB (R) – This bit indicates that a Set Device Bits FIS has been received
Bit [22]: pterr (R) – This bit indicates that a Protocol Error has occurred. An interrupt will be generated if bit
20 of SIEN is set.
Bit [21]: Scr_dis (R/W)– This bit disables the scrambling of data on the serial ATA bus. This is used only for
debugging purposes and should not be changed by the user
相关PDF资料 |
PDF描述 |
|---|---|
| SII3114CTU | PCI BUS CONTROLLER, PQFP176 |
| SII3124ACBHU | PCI BUS CONTROLLER, PBGA364 |
| SII3512ECTU128 | PCI BUS CONTROLLER, PQFP128 |
| SII3531ACNU | PCI BUS CONTROLLER, QCC48 |
| SIO10N268-NU | MULTIFUNCTION PERIPHERAL, PQFP128 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SII3114CTU | 制造商:Silicon Image Inc 功能描述:PCI to Serial ATA Controller 176-Pin TQFP 制造商:SILICON 功能描述: |
| SII3124A | 制造商:SILICONIMAGE 制造商全称:SILICONIMAGE 功能描述:PCI-X to Serial ATA Controller |
| SII3124ACBHU | 制造商:SILICONIMAGE 制造商全称:SILICONIMAGE 功能描述:PCI-X to Serial ATA Controller |
| SII3132 | 制造商:SILICONIMAGE 制造商全称:SILICONIMAGE 功能描述:PCI Express to 2-Port Serial ATA II Host Controller |
| SII3132CNU | 制造商:Silicon Image Inc 功能描述:PCI Express to Serial ATA Controller 88-Pin QFN |
发布紧急采购，3分钟左右您将得到回复。