参数资料
型号: SII3114CT176
元件分类: 总线控制器
英文描述: PCI BUS CONTROLLER, PQFP176
封装: TQFP-176
文件页数: 78/127页
文件大小: 564K
代理商: SII3114CT176
SiI3114 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
SiI-DS-0103-D
46
2007 Silicon Image, Inc.
Internal Register Space – Base Address 5
These registers are 32-bits wide and define the internal operation of the SiI3114. The access types are defined as
follows: R=read, W=write, and C=clearable by some write operation. Access to this register is through the PCI
Memory space. Base Address 5 accesses can be disabled by setting input BA5_EN low. Table 22 shows the
internal register space for base 5 addresses.
Table 22. SiI3114 Internal Register Space – Base Address 5
Register Name
Address
Offset
31
16
15
00
Access
Type
00H
Reserved
PCI Bus Master
Status – Channel
0
Software Data
PCI Bus Master
Command –
Channel 0
R/W
04H
PRD Table Address – Channel 0
R/W
08H
Reserved
PCI Bus Master
Status – Channel
1
Reserved
PCI Bus Master
Command –
Channel 1
R/W
0CH
PRD Table Address – Channel 1
R/W
10H
PCI Bus Master
Status – Channel
1
PCI Bus Master
Status2 – Channel
0
Software Data
PCI Bus Master
Command2 –
Channel 0
R/W
14H
Reserved
-
18H
Reserved
PCI Bus Master
Status2 – Channel
1
Reserved
PCI Bus Master
Command2 –
Channel 1
R/W
1CH
Reserved
-
20H
PRD Address – Channel 0
R
24H
PCI Bus Master Byte Count – Channel 0
R
28H
PRD Address – Channel 1
R
2CH
PCI Bus Master Byte Count – Channel 1
R
30H
Reserved
-
34H
Reserved
-
38H
Reserved
-
3CH
Reserved
-
40H
FIFO Valid Byte Count – Channel 0
FIFO Wr Request
Control – Channel
0
FIFO Rd Request
Control – Channel
0
R/W
44H
FIFO Valid Byte Count – Channel 1
FIFO Wr Request
Control – Channel
1
FIFO Rd Request
Control – Channel
1
R/W
48H
System Configuration Status
System Command
R/W
4CH
System Software Data
R/W
50H
Flash Memory Address – Command and Status
R/W
54H
Reserved
GPIO Control
Flash Memory
Data
R/W
58H
EEPROM Memory Address – Command and Status
R/W
5CH
Reserved
EEPROM Memory
Data
R/W
60H
FIFO Port – Channel 0
R/W
64H
Reserved
-
68H
FIFO Byte1 Write
Pointer – Channel
0
FIFO Byte1 Read
Pointer – Channel
0
FIFO Byte0 Write
Pointer – Channel
0
FIFO Byte0 Read
Pointer – Channel
0
R
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