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参数资料
| 型号： | SII3114CT176 |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP176 |
| 封装： | TQFP-176 |
| 文件页数： | 121/127页 |
| 文件大小： | 564K |
| 代理商： | SII3114CT176 |
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SiI3114 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
2007 Silicon Image, Inc.
85
SiI-DS-0103-D
FIS Support
FIS Summary
Table 29 summarizes the implementation of FIS Support. Note that 14 FIS codes meet the criteria of FIS code
selection in Serial ATA, and 8 out of the 14 are already defined.
Table 29. FIS Summary
FIS
Code
FIS Name
Host to
Device
to Host
Comment
27h
Register (Host to Device)
√
-
Support Expanded Registers
HOB not sent to device (device dongle ignores HOB received)
Can be individually controlled via PCI registers - default to
reject
34h
Register (Device to Host)
-
√
Support Expanded Registers
Host to Device transmission is possible as Transparent.
Can be individually controlled via PCI registers - default to
accept
39h
DMA Activate
-
√
Supported per Serial ATA specification.
Host to Device transmission is possible as Transparent.
Can be individually controlled via PCI registers - default to
accept
41h
DMA Setup
√
On reception, the first 7 dwords of any FIS can be read directly
by the PCI.
Transmission: As transparent FIS
Can be individually controlled via PCI registers - default to
reject
46h
Data
√
Supported per Serial ATA specification.
Can be individually controlled via PCI registers - default to
accept
58h
BIST Activate
√
Support for reception of Far-End Retimed Loopback. No
transmission supported.
Can be individually controlled via PCI registers - default to
accept for Far-End Retimed Loopback; default to reject for all
other BIST types
5Fh
PIO Setup
-
√
Supported per Serial ATA specification.
Host to Device transmission is possible as Transparent.
Can be individually controlled via PCI registers - default to
accept
A1h
Set Device Bits
-
√
Supported per Serial ATA specification
Host to Device transmission is possible as Transparent
Can be individually controlled via PCI registers - default to
accept
A6h
Reserved
TBD
B8h
Reserved
TBD
BFh
Reserved
TBD
C7h
Reserved
TBD
D4h
Reserved
TBD
D9h
Reserved
TBD
Supported as one group of unrecognized FIS, together with
other unsupported FISes, such as "Others" below, and FIS
Code 27h in the reception direction.
Can be individually controlled via PCI registers - default to
reject
Others Reserved
TBD
Supported as one group of unrecognized FIS, together with
other unsupported FISes (FIS Code 27h, A6h, B8h, BFh, C7h,
D4h, D9h) in the reception direction.
All "Others" are controlled as a group via PCI registers -
default to reject
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