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参数资料
| 型号： | SII3114CT176 |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP176 |
| 封装： | TQFP-176 |
| 文件页数： | 31/127页 |
| 文件大小： | 564K |
| 代理商： | SII3114CT176 |
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SiI3114 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
SiI-DS-0103-D
118
2007 Silicon Image, Inc.
EEPROM Memory Access
The SiI3114 supports an external 256-byte EEPROM memory device. Access to the EEPROM memory is
available through internal register operations in the SiI3114.
EEPROM Write Operation
Verify that bit 25 is cleared in the EEPROM Memory Address – Command + Status register at Offset 58H
of Base Address 5. The bit reads one when a memory access is currently in progress. It reads zero when
the memory access is complete and ready for another operation.
Write ‘1’ to clear bit 28 in the EEPROM Memory Address – Command + Status register. The bit is set if an
error occurred during a previous memory access.
Program the write address for the EEPROM memory access. The address field is defined by bits [07:00]
in the EEPROM Memory Address – Command + Status register. Program bits [15:08] to zero.
Program the write data for the EEPROM memory access. The data field is defined by bits [07:00] in the
EEPROM Memory Data register at Offset 5CH of Base Address 5.
Program the memory access type. The memory access type is defined by bit 24 in the EEPROM Memory
Address – Command + Status register. The bit must be cleared for a memory write access.
Initiate the EEPROM memory access by setting bit 25 in the EEPROM Memory Address – Command +
Status register.
Poll bit 25 in the EEPROM Memory Address – Command + Status register. The bit reads one when a
memory access is currently in progress. It reads zero when the memory access is complete.
Check bit 28 in the EEPROM Memory Address – Command + Status register. The bit is set if an error
occurred during a previous memory access.
EEPROM Read Operation
Verify that bit 25 is cleared in the EEPROM Memory Address – Command + Status register at Offset 58H
of Base Address 5. The bit reads one when a memory access is currently in progress. It reads zero when
the memory access is complete and ready for another operation.
Write ‘1’ to clear bit 28 in the EEPROM Memory Address – Command + Status register. The bit is set if an
error occurred during a previous memory access.
Program the read address for the EEPROM memory access. The address field is defined by bits [07:00]
in the EEPROM Memory Address – Command + Status register. Program bits [15:08] to zero.
Program the memory access type. The memory access type is defined by bit 24 in the EEPROM Memory
Address – Command + Status register. The bit must be set for a memory read access.
Initiate the EEPROM memory access by setting bit 25 in the EEPROM Memory Address – Command +
Status register.
Poll bit 25 in the EEPROM Memory Address – Command + Status register. The bit reads one when a
memory access is currently in progress. It reads zero when the memory access is complete.
Check bit 28 in the EEPROM Memory Address – Command + Status register. The bit is set if an error
occurred during a previous memory access.
Read the data from the EEPROM memory access. The data field is defined by bits [07:00] in the
EEPROM Memory Data register at Offset 5CH of Base Address 5.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SII3114CTU | 制造商:Silicon Image Inc 功能描述:PCI to Serial ATA Controller 176-Pin TQFP 制造商:SILICON 功能描述: |
| SII3124A | 制造商:SILICONIMAGE 制造商全称:SILICONIMAGE 功能描述:PCI-X to Serial ATA Controller |
| SII3124ACBHU | 制造商:SILICONIMAGE 制造商全称:SILICONIMAGE 功能描述:PCI-X to Serial ATA Controller |
| SII3132 | 制造商:SILICONIMAGE 制造商全称:SILICONIMAGE 功能描述:PCI Express to 2-Port Serial ATA II Host Controller |
| SII3132CNU | 制造商:Silicon Image Inc 功能描述:PCI Express to Serial ATA Controller 88-Pin QFN |
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