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参数资料
型号： SII3114CT176
元件分类： 总线控制器
英文描述： PCI BUS CONTROLLER, PQFP176
封装： TQFP-176
文件页数： 107/127页
文件大小： 564K
代理商： SII3114CT176
SiI3114 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
SiI-DS-0103-D
72
2007 Silicon Image, Inc.
Bit[18:14]: Reserved. The values of these bits should not be changed from their defaults otherwise erratic
operation may result
Bit[13]: Tx_Swing_0: This bit, together with Tx_Swing_1, sets the nominal output swing for the Transmitter.
The available combinations are as follows:
Tx_Swing_1
Tx_Swing_0
Nominal Output Swing
0
500mV
0
1
600mV
1
0
700mV
1
800mV
Bit[12:0]: Reserved. The values of these bits should not be changed from their defaults otherwise erratic
operation may result.
SIEN
Address Offset: 148H / 1C8H / 348H / 3C8H
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
R
e
served
Transmit
_OK
IFIS_OK
Int
rlckFIS
P
M
CHG
F
R
e
served
S
DB
H
C
pterr
B
W
R
e
served
N
Reserved
This register contains bits for enabling interrupts.
Bit [31:30]: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [29]: Transmit_OK – This bit enables an interrupt upon the assertion of the Transmit_OK bit in the
SMisc register.
Bit [28]: IFIS_OK – This bit enables an interrupt upon the assertion of the IFIS_OK bit in the SMisc
register.
Bit [27]: IntrlckFIS – This bit enables an interrupt upon the assertion of the IntrlckFIS bit in the SMisc
register.
Bit [26]: PMCHG – This bit enables an interrupt upon a Power Management Mode change. The interrupt is
reported in bit 6 of SMisc.
Bit [25]: F – This bit enables an interrupt upon the assertion of the F bit in the DIAG field of the SError
register.
Bit [24]: Reserved (R). This bit is reserved and returns zero on a read.
Bit [23]: SDB – This bit enables an interrupt upon the assertion of the SDB bit in the SMisc register.
Bit [22]: H – This bit enables an interrupt upon the assertion of the H bit in the DIAG field of the SError
register.
Bit [21]: C – This bit enables an interrupt upon the assertion of the C bit in the DIAG field of the SError
register.
Bit [20]: pterr – This bit enables the Pterr interrupt reported in SMisc bit 22.
Bit [19]: B – This bit enables an interrupt upon the assertion of the B bit in the DIAG field of the SError
register.
Bit [18]: W – This bit enables an interrupt upon the assertion of the W bit in the DIAG field of the SError
register.
Bit [17]: Reserved (R). This bit is reserved and returns zeros on a read.
Bit [16]: N – This bit enables an interrupt upon the assertion of the N bit in the DIAG field of the SError
register.
Bit [15:00]: Reserved (R). This bit field is reserved and returns zeros on a read.
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