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参数资料
型号： SII3114CT176
元件分类： 总线控制器
英文描述： PCI BUS CONTROLLER, PQFP176
封装： TQFP-176
文件页数： 58/127页
文件大小： 564K
代理商： SII3114CT176
SiI3114 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
SiI-DS-0103-D
28
2007 Silicon Image, Inc.
Bit [03]: Special Cycles (R) – Special Cycles Enable. This bit is hardwired to 0 to indicate that the SiI3114
does not respond to Special Cycles.
Bit [02]: Bus Master (R/W) – Bus Master Enable. This bit set enables the SiI3114 to act as PCI bus master.
Bit [01]: Memory Space (R/W) – Memory Space Enable. This bit set enables the SiI3114 to respond to PCI
memory space access.
Bit [00]: IO Space (R/W) – IO Space Enable. This bit set enables the SiI3114 to respond to PCI IO space
access.
PCI Class Code – Revision ID
Address Offset: 08H
Access Type: Read/Write
Reset Value: 0x0180_0002 or 0x0104_0002
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
PCI Class Code
Revision ID
This register defines the various control functions associated with the PCI bus. The register bits are defined
below.
Bit [31:08]: PCI Class Code (R) – PCI Class Code. This value in this bit field is determined by any one of
three options:
1) The default value, set by an external jumper on the FL_ADDR[00]/CLASS_SEL pin:
If CLASS_SEL = 0, the value is 010400h for RAID mode
If CLASS_SEL = 1, the value is 018000h for Mass Storage class
2) Loaded from an external memory device: If an external memory device — flash or EEPROM — is
present with the correct signature, the PCI Class Code is loaded from that device after reset. See
“Auto-Initialization” section on page 22 for more information.
3) System programmable : If Bit 0 of the Configuration register (40H) is set the three bytes are system
programmable.
Bit [07:00]: Revision ID (R) – Chip Revision ID. This bit field is hardwired to 02
H for the production chip.
BIST – Header Type – Latency Timer – Cache Line Size
Address Offset: 0CH
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
BIST
Header Type
Latency Timer
Cache Line Size
This register defines the various control functions associated with the PCI bus. The register bits are defined
below.
Bit [31:24]: BIST (R). This bit field is hardwired to 00
H.
Bit [23:16]: Header Type (R). This bit field is hardwired to 00
H.
Bit [15:08]: Latency Timer (R/W). This bit field is used to specify the time in number of PCI clocks, the
SiI3114 as a master is still allowed to control the PCI bus after its GRANT_L is deasserted. The lower four
bits [0B:08] are hardwired to 0H, resulting in a time granularity of 16 clocks.
Bit [07:00]: Cache Line Size (R/W). This bit field is used to specify the system cacheline size in terms of
32-bit words. The upper 2 bits are not used, resulting a maximum size of 64 32-bit words. With the SiI3114
as a master, initiating a read transaction, it issues PCI command Read Multiple in place, when empty
space in its FIFO is larger than the value programmed in this register.
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相关代理商/技术参数
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