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参数资料
| 型号： | SII3114CT176 |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP176 |
| 封装： | TQFP-176 |
| 文件页数： | 30/127页 |
| 文件大小： | 564K |
| 代理商： | SII3114CT176 |
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SiI3114 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
2007 Silicon Image, Inc.
117
SiI-DS-0103-D
Flash and EEPROM Programming Sequences
Flash Memory Access
The SiI3114 supports an external flash memory device up to 4 Mbit in capacity. Access to the Flash memory is
available through two means: PCI Direct Access and Register Access.
PCI Direct Access
Access to the Expansion Rom is enabled by setting bit 0 in the Expansion Rom Base Address register at Offset
30h of the PCI Configuration Space. When this bit is set, bits [31:19] of the same register are programmable by
the system to set the base address for all Flash memory accesses. Read and write operations with the flash
memory are initiated by Memory Read and Memory Write commands on the PCI bus. Accesses may be as bytes,
words, or dwords.
Register Access
This type of flash memory access is carried out through a sequence of internal register read and write operations.
The proper programming sequences are detailed below.
Flash Write Operation
Verify that bit 25 is cleared in the register at Offset 50H of Base Address 5. The bit reads one when a
memory access is currently in progress.
It reads zero when the memory access is complete and ready for another operation.
Program the write address for the Flash memory access. The address field is defined by bits [18:00] in
the Flash Memory Address – Command + Status register.
Program the write data for the Flash memory access. The data field is defined by bits [07:00] in the Flash
Memory Data register at Offset 54 of Base Address 5.
Program the memory access type. The memory access type is defined by bit 24 in the Flash Memory
Address – Command + Status register. The bit must be cleared for a memory write access.
Initiate the Flash memory access by setting bit 25 in the Flash Memory Address – Command + Status
register.
Flash Read Operation
Verify that bit 25 is cleared in the Flash Memory Address – Command + Status register at Offset 50H of
Base Address 5. The bit reads one when a memory access is currently in progress. It reads zero when
the memory access is complete and ready for another operation.
Program the read address for the Flash memory access. The address field is defined by bits [18:00] in
the Flash Memory Address – Command + Status register.
Program the memory access type. The memory access type is defined by bit 24 in the Flash Memory
Address – Command + Status register. The bit must be set for a memory read access.
Initiate the Flash memory access by setting bit 25 in the Flash Memory Address – Command + Status
register.
Verify that bit 25 is cleared in the Flash Memory Address – Command + Status register. The bit reads one
when a memory access is currently in progress. It reads zero when the memory access is complete.
Read the data from the Flash memory access. The data field is defined by bits [07:00] in the Flash
Memory Data register at Offset 54H of Base Address 5.
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相关代理商/技术参数 |
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|---|---|
| SII3114CTU | 制造商:Silicon Image Inc 功能描述:PCI to Serial ATA Controller 176-Pin TQFP 制造商:SILICON 功能描述: |
| SII3124A | 制造商:SILICONIMAGE 制造商全称:SILICONIMAGE 功能描述:PCI-X to Serial ATA Controller |
| SII3124ACBHU | 制造商:SILICONIMAGE 制造商全称:SILICONIMAGE 功能描述:PCI-X to Serial ATA Controller |
| SII3132 | 制造商:SILICONIMAGE 制造商全称:SILICONIMAGE 功能描述:PCI Express to 2-Port Serial ATA II Host Controller |
| SII3132CNU | 制造商:Silicon Image Inc 功能描述:PCI Express to Serial ATA Controller 88-Pin QFN |
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