- 您现在的位置：买卖IC网 > PDF目录98080 > SII3114CT176 PCI BUS CONTROLLER, PQFP176 PDF资料下载
参数资料
| 型号： | SII3114CT176 |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP176 |
| 封装： | TQFP-176 |
| 文件页数： | 87/127页 |
| 文件大小： | 564K |
| 代理商： | SII3114CT176 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页当前第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页
SiI3114 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
SiI-DS-0103-D
54
2007 Silicon Image, Inc.
Bit [03]: PBM Rd-Wr (R/W) – PCI Bus Master Read-Write Control. This bit is set to specify a DMA write
operation from Channel X to system memory. This bit is cleared to specify a DMA read operation from
system memory to the Channel X device.
Bit [02]: Reserved (R). This bit is reserved and returns zero on a read.
Bit [01]: Interrupt Steering (R/W). This bit is set to 1 to allow interrupts from all four channels. If the bit is a
0 (the default), only interrupts from the channel selected by the “shadow” Device Select bit are enabled.
This bit appears only in the Channel 2 (offset 200H) register; this bit is reserved in the Channel 0 (offset
00H), Channel 1 (offset 08H), and Channel 3 (offset 208H) registers.
Bit [00]: PBM Enable (R/W) – PCI Bus Master Enable – Channel X. This bit is set to enable PCI bus
master operations for Channel X. PCI bus master operations can be halted by clearing this bit, but will
erase all state information in the control logic. If this bit is cleared while the PCI bus master is active, the
operation will be aborted and the data discarded. While this bit is set, accessing Channel X Task File or
PIO data registers will be terminated with Target-Abort.
PRD Table Address – Channel X
Address Offset: 04H / 0CH / 204H / 20CH
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
PRD Table Address
R
e
served
This register defines the PRD Table Address register for Channel X in the SiI3114. The register bits are defined
below.
Bit [31:02]: PRD Table Address (R/W) – Physical Region Descriptor Table Address. This bit field defines
the Descriptor Table base address.
Bit [01:00]: Reserved (R). This bit field is reserved and returns zeros on a read.
PCI Bus Master2 – Channel X
Address Offset: 10H / 18H / 210H / 218H
Access Type: Read/Write
Reset Value: 0x0808_XX00 (Chnl 0/2) / 0x0008_0000 (Chnl 1/3)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Chnl
X+
1
PB
M
Simplex
Chnl
X+
1
P
B
M
DMA
Ca
p
0
Chnl
X+
1
P
B
M
DMA
Ca
p
1
Chnl
X+
1
Watchdog
Chnl
X+
1
Buffe
rE
m
pty
Chnl
X+
1
DMA
Comp
Chnl
X+
1
PBM
Error
Chnl
X+
1
P
B
M
Ac
ti
v
e
Watchdog
Chnl
X+
1
DMA
Comp
Software
R
eserved
SA
TA
IN
T
X+
1
R
eserved
Reserved for Chnl 1/3
Chnl
X
PB
M
Simplex
Chnl
X
P
B
M
DMA
Ca
p
1
Chnl
X
P
B
M
DMA
Ca
p
0
Chnl
X
Watchdog
Chnl
X
Buffe
rE
m
pty
Chnl
X
DMA
Comp
Chnl
X
PBM
Error
Chnl
X
P
B
M
Ac
ti
v
e
Reserved for Chnl 1/3
SA
TA
IN
T
X
P
B
M
Rd-Wr
R
eserved
PB
M
Enable
This register defines the second PCI bus master register for Channel X in the SiI3114. The system must access
these register bits through this address to enable the Large Block Transfer Mode.
The register bits are defined below.
Bit [31:24]: (R) These bits are copies of PCI Bus Master Channel X+1 bits. This bit field (and bits 15 to 5)
appears only in the Channel 0 (offset 10H) and Channel 2 (offset 210H) registers; this bit field is reserved in
the Channel 1 (offset 18H) and Channel 3 (offset 218H) registers.
Bit [23]: PBM Simplex (R) – PCI Bus Master Simplex Only. This read-only bit field is hardwired to zero to
indicate that all channels can operate as PCI bus master at any time.
相关PDF资料 |
PDF描述 |
|---|---|
| SII3114CTU | PCI BUS CONTROLLER, PQFP176 |
| SII3124ACBHU | PCI BUS CONTROLLER, PBGA364 |
| SII3512ECTU128 | PCI BUS CONTROLLER, PQFP128 |
| SII3531ACNU | PCI BUS CONTROLLER, QCC48 |
| SIO10N268-NU | MULTIFUNCTION PERIPHERAL, PQFP128 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SII3114CTU | 制造商:Silicon Image Inc 功能描述:PCI to Serial ATA Controller 176-Pin TQFP 制造商:SILICON 功能描述: |
| SII3124A | 制造商:SILICONIMAGE 制造商全称:SILICONIMAGE 功能描述:PCI-X to Serial ATA Controller |
| SII3124ACBHU | 制造商:SILICONIMAGE 制造商全称:SILICONIMAGE 功能描述:PCI-X to Serial ATA Controller |
| SII3132 | 制造商:SILICONIMAGE 制造商全称:SILICONIMAGE 功能描述:PCI Express to 2-Port Serial ATA II Host Controller |
| SII3132CNU | 制造商:Silicon Image Inc 功能描述:PCI Express to Serial ATA Controller 88-Pin QFN |
发布紧急采购，3分钟左右您将得到回复。