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参数资料
| 型号： | SPC5634MF1MMG80 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 112/122页 |
| 文件大小： | 0K |
| 描述： | IC MCU FLASH 1.5M 94K 208-PBGA |
| 标准包装： | 90 |
| 系列： | MPC56xx Qorivva |
| 核心处理器： | e200z3 |
| 芯体尺寸： | 32-位 |
| 速度： | 80MHz |
| 连通性： | CAN，EBI/EMI，LIN，SCI，SPI，UART/USART |
| 外围设备： | DMA，POR，PWM，WDT |
| 输入/输出数： | 114 |
| 程序存储器容量： | 1.5MB（1.5M x 8） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 94K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 4.5 V ~ 5.25 V |
| 数据转换器： | A/D 34x12b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 150°C |
| 封装/外壳： | 208-BGA |
| 包装： | 托盘 |
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Introduction
MPC5634M Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
9
1
Introduction
1.1
Document overview
This document provides an overview and describes the features of the MPC5634M series of microcontroller units (MCUs). For
functional characteristics, refer to the device reference manual. Electrical specifications and package mechanical drawings are
included in this device data sheet. Pin assignments can be found in both the reference manual and data sheet.
1.2
Description
These 32-bit automotive microcontrollers are a family of system-on-chip (SoC) devices that contain all the features of the
MPC5500 family and many new features coupled with high performance 90 nm CMOS technology to provide substantial
reduction of cost per feature and significant performance improvement. The advanced and cost-efficient host processor core of
this automotive controller family is built on Power Architecture technology. This family contains enhancements that improve
the architecture’s fit in embedded applications, includes additional instruction support for digital signal processing (DSP),
integrates technologies—such as an enhanced time processor unit, enhanced queued analog-to-digital converter, Controller
Area Network, and an enhanced modular input-output system—that are important for today’s lower-end powertrain
applications. This device family is a completely compatible extension to Freescale’s MPC5500 family. The device has a single
level of memory hierarchy consisting of up to 94 KB on-chip SRAM and up to 1.5 MB of internal flash memory. The device
also has an external bus interface (EBI) for ‘calibration’. This external bus interface has been designed to support most of the
standard memories used with the MPC5xx and MPC55xx families.
2
Overview
This document provides electrical specifications, pin assignments, and package diagrams for the MPC5634M series of
microcontroller units (MCUs). For functional characteristics, refer to the MPC5634M Microcontroller Reference Manual.
The MPC5634M series microcontrollers are system-on-chip devices that are built on Power Architecture technology and:
Are 100% user-mode compatible with the Power Architecture instruction set
Contain enhancements that improve the architecture’s fit in embedded applications
Include additional instruction support for digital signal processing (DSP)
Integrate technologies such as an enhanced time processor unit, enhanced queued analog-to-digital converter,
Controller Area Network, and an enhanced modular input-output system
2.1
Device comparison
2.2
MPC5634M feature details
2.2.1
e200z335 core
The e200z335 processor utilizes a four stage pipeline for instruction execution. The Instruction Fetch (stage 1), Instruction
Decode/Register file Read/Effective Address Calculation (stage 2), Execute/Memory Access (stage 3), and Register Writeback
(stage 4) stages operate in an overlapped fashion, allowing single clock instruction execution for most instructions.
The integer execution unit consists of a 32-bit Arithmetic Unit (AU), a Logic Unit (LU), a 32-bit Barrel shifter (Shifter), a
Mask-Insertion Unit (MIU), a Condition Register manipulation Unit (CRU), a Count-Leading-Zeros unit (CLZ), a 32
32
Hardware Multiplier array, result feed-forward hardware, and support hardware for division.
Most arithmetic and logical operations are executed in a single cycle with the exception of the divide instructions. A
Count-Leading-Zeros unit operates in a single clock cycle. The Instruction Unit contains a PC incrementer and a dedicated
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