参数资料
型号: SPC5634MF1MMG80
厂商: Freescale Semiconductor
文件页数: 7/122页
文件大小: 0K
描述: IC MCU FLASH 1.5M 94K 208-PBGA
标准包装: 90
系列: MPC56xx Qorivva
核心处理器: e200z3
芯体尺寸: 32-位
速度: 80MHz
连通性: CAN,EBI/EMI,LIN,SCI,SPI,UART/USART
外围设备: DMA,POR,PWM,WDT
输入/输出数: 114
程序存储器容量: 1.5MB(1.5M x 8)
程序存储器类型: 闪存
RAM 容量: 94K x 8
电压 - 电源 (Vcc/Vdd): 4.5 V ~ 5.25 V
数据转换器: A/D 34x12b
振荡器型: 内部
工作温度: -40°C ~ 150°C
封装/外壳: 208-BGA
包装: 托盘
MPC5634M Microcontroller Data Sheet, Rev. 9
Electrical characteristics
Freescale Semiconductor
104
4.16.6
eQADC SSI timing
Figure 29. eQADC SSI timing
Table 41. eQADC SSI timing characteristics (pads at 3.3 V or at 5.0 V)1
1 SS timing specified at fSYS = 80 MHz, VDD = 1.14 V to 1.32 V, VDDEH = 4.5 V to 5.25 V, TA = TL to TH, and CL =50pF
with SRC = 0b00.
CLOAD = 25pF on all outputs. Pad drive strength set to maximum.
#
Symbol
C
Rating
Min
Typ
Max
Unit
1fFCK
CC
D
FCK Frequency 2, 3
2 Maximum operating frequency is highly dependent on track delays, master pad delays, and slave pad delays.
3 FCK duty is not 50% when it is generated through the division of the system clock by an odd number.
1/17 fSYS_CLK
1
2 fSYS_CLK
Hertz
1tFCK
CC
D
FCK Period (tFCK = 1/ fFCK)
2 tSYS_CLK
17tSYS_CLK
seconds
2tFCKHT CC
D
Clock (FCK) High Time
tSYS_CLK 6.5
9* tSYS_CLK 6.5
ns
3tFCKLT CC
D
Clock (FCK) Low Time
tSYS_CLK 6.5
8* tSYS_CLK 6.5
ns
4tSDS_LL CC
D
SDS Lead/Lag Time
–7.5
+7.5
ns
5tSDO_LL CC
D
SDO Lead/Lag Time
–7.5
+7.5
ns
6tDVFE CC
D
Data Valid from FCK Falling Edge
(tFCKLT+tSDO_LL)
1ns
7tEQ_SU CC
D
eQADC Data Setup Time (Inputs)
22
ns
8tEQ_HO CC
D
eQADC Data Hold Time (Inputs)
1
ns
1st (MSB)
2nd
25th
26th
1st (MSB)
2nd
25th
26th
8
7
5
6
5
4
3
1
3
2
1
2
FCK
SDS
SDO
External Device Data Sample at
SDI
eQADC Data Sample at
FCK Falling Edge
FCK Rising Edge
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