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| 型号： | SPC5634MF1MMG80 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 31/122页 |
| 文件大小： | 0K |
| 描述： | IC MCU FLASH 1.5M 94K 208-PBGA |
| 标准包装： | 90 |
| 系列： | MPC56xx Qorivva |
| 核心处理器： | e200z3 |
| 芯体尺寸： | 32-位 |
| 速度： | 80MHz |
| 连通性： | CAN，EBI/EMI，LIN，SCI，SPI，UART/USART |
| 外围设备： | DMA，POR，PWM，WDT |
| 输入/输出数： | 114 |
| 程序存储器容量： | 1.5MB（1.5M x 8） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 94K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 4.5 V ~ 5.25 V |
| 数据转换器： | A/D 34x12b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 150°C |
| 封装/外壳： | 208-BGA |
| 包装： | 托盘 |
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MPC5634M Microcontroller Data Sheet, Rev. 9
Overview
Freescale Semiconductor
16
Sets up the MMU to allow user boot code to execute as either Power Architecture code (default) or as Freescale VLE
code
Detection of user boot code
Automatic switch to serial boot mode if internal flash is blank or invalid
Supports user programmable 64-bit password protection for serial boot mode
Supports serial bootloading via FlexCAN bus and eSCI using Freescale protocol
Supports serial bootloading via FlexCAN bus and eSCI with auto baud rate sensing
Supports serial bootloading of either Power Architecture code (default) or Freescale VLE code
Supports booting from calibration bus interface
Supports censorship protection for internal flash memory
Provides an option to enable the core watchdog timer
Provides an option to disable the software watchdog timer
2.2.12
eMIOS
The eMIOS (Enhanced Modular Input Output System) module provides the functionality to generate or measuretime events.
The channels on this module provide a range of operating modes including the capability to perform dual input capture or dual
output compare as well as PWM output.
The eMIOS provides the following features:
16 channels (24-bit timer resolution)
For compatibility with other family members selected channels and timebases are implemented:
— Channels 0 to 6, 8 to 15, and 23
— Timebases A, B and C
Channels 1, 3, 5 and 6 support modes:
— General Purpose Input/Output (GPIO)
— Single Action Input Capture (SAIC)
— Single Action Output Compare (SAOC)
Channels 2, 4, 11 and 13 support all the modes above plus:
— Output Pulse Width Modulation Buffered (OPWMB)
Channels 0, 8, 9, 10, 12, 14, 15, 23 support all the modes above plus:
— Input Period Measurement (IPM)
— Input Pulse Width Measurement (IPWM)
— Double Action Output Compare (set flag on both matches) (DAOC)
— Modulus Counter Buffered (MCB)
— Output Pulse Width and Frequency Modulation Buffered (OPWFMB)
Three 24-bit wide counter buses
— Counter bus A can be driven by channel 23 or by the eTPU2 and all channels can use it as a reference
— Counter bus B is driven by channel 0 and channels 0 to 6 can use it as a reference
— Counter bus C is driven by channel 8 and channels 8 to 15 can use it as a reference
Shared time bases with the eTPU2 through the counter buses
Synchronization among internal and external time bases
2.2.13
eTPU2
The eTPU2 is an enhanced co-processor designed for timing control. Operating in parallel with the host CPU, eTPU2 processes
instructions and real-time input events, performs output waveform generation, and accesses shared data without host
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