参数资料
型号: SPC5634MF1MMG80
厂商: Freescale Semiconductor
文件页数: 57/122页
文件大小: 0K
描述: IC MCU FLASH 1.5M 94K 208-PBGA
标准包装: 90
系列: MPC56xx Qorivva
核心处理器: e200z3
芯体尺寸: 32-位
速度: 80MHz
连通性: CAN,EBI/EMI,LIN,SCI,SPI,UART/USART
外围设备: DMA,POR,PWM,WDT
输入/输出数: 114
程序存储器容量: 1.5MB(1.5M x 8)
程序存储器类型: 闪存
RAM 容量: 94K x 8
电压 - 电源 (Vcc/Vdd): 4.5 V ~ 5.25 V
数据转换器: A/D 34x12b
振荡器型: 内部
工作温度: -40°C ~ 150°C
封装/外壳: 208-BGA
包装: 托盘
MPC5634M Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
4
Frequency Modulating Phase-locked loop (FMPLL)
— Reference clock pre-divider (PREDIV) for finer frequency synthesis resolution
— Reduced frequency divider (RFD) for reducing the FMPLL output clock frequency without forcing the FMPLL
to re-lock
— System clock divider (SYSDIV) for reducing the system clock frequency in normal or bypass mode
— Input clock frequency range from 4 MHz to 20 MHz before the pre-divider, and from 4 MHz to 16 MHz at the
FMPLL input
— Voltage controlled oscillator (VCO) range from 256 MHz to 512 MHz
— VCO free-running frequency range from 25 MHz to 125 MHz
— Four bypass modes: crystal or external reference with PLL on or off
— Two normal modes: crystal or external reference
— Programmable frequency modulation
– Triangle wave modulation
– Register programmable modulation frequency and depth
— Lock detect circuitry reports when the FMPLL has achieved frequency lock and continuously monitors lock status
to report loss of lock conditions
– User-selectable ability to generate an interrupt request upon loss of lock
– User-selectable ability to generate a system reset upon loss of lock
— Clock quality monitor (CQM) module provides loss-of-clock detection for the FMPLL reference and output
clocks
– User-selectable ability to generate an interrupt request upon loss of clock
– User-selectable ability to generate a system reset upon loss of clock
– Backup clock (reference clock or FMPLL free-running) can be applied to the system in case of loss of clock
Calibration bus interface (EBI)
— Available only in the calibration package (496 CSP package)
— 1.8 V to 3.3 V ± 10% I/O (1.6 V to 3.6 V)
— Memory controller with support for various memory types
— 16-bit data bus, up to 22-bit address bus
— Selectable drive strength
— Configurable bus speed modes
— Bus monitor
— Configurable wait states
System integration unit (SIU)
— Centralized GPIO control of 80 I/O pins
— Centralized pad control on a per-pin basis
– Pin function selection
– Configurable weak pull-up or pull-down
–Drive strength
–Slew rate
– Hysteresis
— System reset monitoring and generation
— External interrupt inputs, filtering and control
— Critical Interrupt control
— Non-Maskable Interrupt control
— Internal multiplexer subblock (IMUX)
– Allows flexible selection of eQADC trigger inputs (eTPU, eMIOS and external signals)
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