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参数资料
| 型号： | SPC5634MF1MMG80 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 32/122页 |
| 文件大小： | 0K |
| 描述： | IC MCU FLASH 1.5M 94K 208-PBGA |
| 标准包装： | 90 |
| 系列： | MPC56xx Qorivva |
| 核心处理器： | e200z3 |
| 芯体尺寸： | 32-位 |
| 速度： | 80MHz |
| 连通性： | CAN，EBI/EMI，LIN，SCI，SPI，UART/USART |
| 外围设备： | DMA，POR，PWM，WDT |
| 输入/输出数： | 114 |
| 程序存储器容量： | 1.5MB（1.5M x 8） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 94K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 4.5 V ~ 5.25 V |
| 数据转换器： | A/D 34x12b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 150°C |
| 封装/外壳： | 208-BGA |
| 包装： | 托盘 |
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Overview
MPC5634M Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
17
intervention. Consequently, for each timer event, the host CPU setup and service times are minimized or eliminated. A powerful
timer subsystem is formed by combining the eTPU2 with its own instruction and data RAM. High-level assembler/compiler
and documentation allows customers to develop their own functions on the eTPU2.
The eTPU2 includes these distinctive features:
The Timer Counter (TCR1), channel logic and digital filters (both channel and the external timer clock input
[TCRCLK]) now have an option to run at full system clock speed or system clock / 2.
Channels support unordered transitions: transition 2 can now be detected before transition 1. Related to this
enhancement, the transition detection latches (TDL1 and TDL2) can now be independently negated by microcode.
A new User Programmable Channel Mode has been added: the blocking, enabling, service request and capture
characteristics of this channel mode can be programmed via microcode.
Microinstructions now provide an option to issue Interrupt and Data Transfer requests selected by channel. They can
also be requested simultaneously at the same instruction.
Channel Flags 0 and 1 can now be tested for branching, in addition to selecting the entry point.
Channel digital filters can be bypassed.
The Timer Counter (TCR1), channel logic and digital filters (both channel and the external timer clock input
[TCRCLK]) now have an option to run at full system clock speed or system clock / 2.
Channels support unordered transitions: transition 2 can now be detected before transition 1. Related to this
enhancement, the transition detection latches (TDL1 and TDL2) can now be independently negated by microcode.
A new User Programmable Channel Mode has been added: the blocking, enabling, service request and capture
characteristics of this channel mode can be programmed via microcode.
Microinstructions now provide an option to issue Interrupt and Data Transfer requests selected by channel. They can
also be requested simultaneously at the same instruction.
Channel Flags 0 and 1 can now be tested for branching, in addition to selecting the entry point.
Channel digital filters can be bypassed.
32 channels, each channel is associated with one input and one output signal
— Enhanced input digital filters on the input pins for improved noise immunity.
— Identical, orthogonal channels: each channel can perform any time function. Each time function can be assigned
to more than one channel at a given time, so each signal can have any functionality.
— Each channel has an event mechanism which supports single and double action functionality in various
combinations. It includes two 24-bit capture registers, two 24-bit match registers, 24-bit greater-equal and
equal-only comparators
— Input and output signal states visible from the host
2 independent 24-bit time bases for channel synchronization:
— First time base clocked by system clock with programmable prescale division from 2 to 512 (in steps of 2), or by
output of second time base prescaler
— Second time base counter can work as a continuous angle counter, enabling angle based applications to match
angle instead of time
— Both time bases can be exported to the eMIOS timer module
— Both time bases visible from the host
Event-triggered microengine:
— Fixed-length instruction execution in two-system-clock microcycle
— 14 KB of code memory (SCM)
— 3 KB of parameter (data) RAM (SPRAM)
— Parallel execution of data memory, ALU, channel control and flow control sub-instructions in selected
combinations
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SPC5634MF2MLQ80 | 制造商:Freescale Semiconductor 功能描述:SPC5634MF2MLQ80 - Bulk |
| SPC5634MF2MLQ80R | 制造商:Freescale Semiconductor 功能描述:1.5M FLASH,94K RAM,E200Z335 - Tape and Reel |
| SPC5634MF2MLU80 | 制造商:Freescale Semiconductor 功能描述:QORIVVA 32-BIT MCU, POWER ARCH CORE, 1.5MB FLASH, 80MHZ, -40 - Trays 制造商:Freescale Semiconductor 功能描述:IC MCU 32BIT 1.5MB FLASH 176QFP |
| SPC5634MF2MLU80R | 制造商:Freescale Semiconductor 功能描述:SPC5634MF2MLU80R - Tape and Reel |
| SPC5634MF2MMG80 | 制造商:Freescale Semiconductor 功能描述:QORIVVA 32-BIT MCU, POWER ARCH, 1.5MB FLASH, 80MHZ, -40/+125 - Trays 制造商:Freescale Semiconductor 功能描述:IC MCU 32BIT 1.5MB FLASH 208BGA |
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