参数资料
型号: SPC5634MF1MMG80
厂商: Freescale Semiconductor
文件页数: 34/122页
文件大小: 0K
描述: IC MCU FLASH 1.5M 94K 208-PBGA
标准包装: 90
系列: MPC56xx Qorivva
核心处理器: e200z3
芯体尺寸: 32-位
速度: 80MHz
连通性: CAN,EBI/EMI,LIN,SCI,SPI,UART/USART
外围设备: DMA,POR,PWM,WDT
输入/输出数: 114
程序存储器容量: 1.5MB(1.5M x 8)
程序存储器类型: 闪存
RAM 容量: 94K x 8
电压 - 电源 (Vcc/Vdd): 4.5 V ~ 5.25 V
数据转换器: A/D 34x12b
振荡器型: 内部
工作温度: -40°C ~ 150°C
封装/外壳: 208-BGA
包装: 托盘
Overview
MPC5634M Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
19
results to the result FIFOs. This allows the ADCs to sample the sensor at a rate high enough to avoid aliasing of out-of-band
noise; while providing a reduced sample rate output to minimize the amount DSP processing bandwidth required to fully
process the digitized waveform.
The eQADC provides the following features:
Dual on-chip ADCs
—2
12-bit ADC resolution
— Programmable resolution for increased conversion speed (12 bit, 10 bit, 8 bit)
– 12-bit conversion time – 1
s (1M sample/sec)
– 10-bit conversion time – 867 ns (1.2M sample/second)
– 8-bit conversion time – 733 ns (1.4M sample/second)
— Up to 10-bit accuracy at 500 KSample/s and 9-bit accuracy at 1 MSample/s
— Differential conversions
— Single-ended signal range from 0 to 5 V
— Variable gain amplifiers on differential inputs (
1, 2, 4)
— Sample times of 2 (default), 8, 64 or 128 ADC clock cycles
— Provides time stamp information when requested
— Parallel interface to eQADC CFIFOs and RFIFOs
— Supports both right-justified unsigned and signed formats for conversion results
Up to 341 input channels (accessible by both ADCs)
23 additional internal channels for measuring control and monitoring voltages inside the device
— Including Core voltage, I/O voltage, LVI voltages, etc.
An internal bandgap reference to allow absolute voltage measurements
4 pairs of differential analog input channels
— Programmable pull-up/pull-down resistors on each differential input for biasing and sensor diagnostic (200 k
,
100 k
, 5 k)
Silicon die temperature sensor
— provides temperature of silicon as an analog value
— read using an internal ADC analog channel
— may be read with either ADC
Decimation Filter
— Programmable decimation factor (2 to 16)
— Selectable IIR or FIR filter
— Up to 4th order IIR or 8th order FIR
— Programmable coefficients
— Saturated or non-saturated modes
— Programmable Rounding (Convergent; Two’s Complement; Truncated)
— Pre-fill mode to pre-condition the filter before the sample window opens
Full duplex synchronous serial interface to an external device
— Free-running clock for use by an external device
— Supports a 26-bit message length
Priority based Queues
— Supports six Queues with fixed priority. When commands of distinct Queues are bound for the same ADC, the
higher priority Queue is always served first
1. 176-pin and 208-pin packages have 34 input channels; 144-pin package has 32.
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