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参数资料
| 型号： | ST7267C8T1/XXX |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, MROM, 30 MHz, RISC MICROCONTROLLER, PQFP48 |
| 封装： | 7 X 7 MM, LEAD FREE, TQFP-48 |
| 文件页数： | 110/189页 |
| 文件大小： | 1643K |
| 代理商： | ST7267C8T1/XXX |
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ST7267C8 ST7267R8
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ST7 POWER SAVING MODES (Cont’d)
5.3 HALT MODE
HALT mode is the lowest power consumption
mode. HALT mode is entered by executing the
HALT
instruction.
The
internal
oscillator
is
stopped, causing all internal processing to be
stopped, including the operation of the on-chip pe-
ripherals.
To further decrease the consumption (especially
for the Suspend mode):
– The internal regulator must be put in powerdown
mode by setting the REG_OFF bit of the CCMR
register.
– The active slew rate compensation cell of the IOs
must be stopped by setting the CPO bit of the
EOSCR register.
Entering HALT mode clears the I bits in the CC
register, enabling interrupts. If an interrupt is pend-
ing, the Device wakes up immediately. Not all in-
terrupts will wake up the Device from HALT, only
those listed in the Interrupt Mapping Table in the
Interrupt section allow wake-up.
Specific interrupts such as an external interrupt or
an USB end of suspend interrupt (as described in
Table 16) or a reset wakes up the Device from
HALT mode.
– If a reset is the wake-up event, the main oscilla-
tor is immediately turned on and a 512 CPU cy-
cle delay is used to stabilize the oscillator. After
the start up delay the device starts in Low power
mode and the CPU resumes operation by fetch-
ing the reset vector.
– If an interrupt is the wake-up event, the main os-
cillator is immediately turned on and a 512 CPU
cycle delay is used to stabilize the oscillator. Af-
ter the start up delay, if the device was in low
power mode before entering in halt mode the de-
vice starts in low power mode and the CPU
resumes operation. But if the device was in full
power mode before entering in halt, the opera-
tion are resumed only after the PLL lock
Refer to Figure 11 for more details.
5.3.1 HALT MODE RECOMMENDATIONS
– Make sure that an external event is available or
that the USB end of suspend interrupt is enabled
to wake up the Device from Halt mode.
– When using an external interrupt to wake up the
Device, reinitialize the corresponding I/O as “In-
put Pull-up with Interrupt” before executing the
HALT instruction. The main reason for this is that
the I/O may be wrongly configured due to exter-
nal interference or by an unforeseen logical con-
dition.
– For the same reason, reinitialize the level sensi-
tiveness of each external interrupt as a precau-
tionary measure.
– The opcode for the HALT instruction is 0x8E. To
avoid an unexpected HALT instruction due to a
program counter failure, it is advised to clear all
occurrences of the data value 0x8E from memo-
ry. For example, avoid defining a constant in
ROM with the value 0x8E.
– As the HALT instruction clears the I bits in the
CC register to allow interrupts, the user may
choose to clear all pending interrupt bits before
executing the HALT instruction. This avoids en-
tering other peripheral interrupt routines after ex-
ecuting the external interrupt routine
corresponding to the wake-up event (reset or ex-
ternal interrupt).
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