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参数资料
| 型号： | ST7267C8T1/XXX |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, MROM, 30 MHz, RISC MICROCONTROLLER, PQFP48 |
| 封装： | 7 X 7 MM, LEAD FREE, TQFP-48 |
| 文件页数： | 23/189页 |
| 文件大小： | 1643K |
| 代理商： | ST7267C8T1/XXX |
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ST7267C8 ST7267R8
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MSCI ST7 INTERFACE (Cont’d)
14.2.6 ST7 Register Description
ALL THESE REGISTERS ARE IN THE ST7 ME-
MEMORY MAP AND CANNOT BE ACCESSED
BY THE MSCI CORE
MSCI CONTROL REGISTER (MCR)
Read / Write
Reset Value: 0000 0001 (01h)
Bit 7:6 = Reserved
Bit 5 = ITRIE ITR Interrupt Enable.
This bit is set and cleared by ST7 software
0: ITR interrupt disabled
1: ITR interrupt enabled
Bit 4 = STPIE Stop Interrupt Enable.
This bit is set and cleared by ST7 software
0: STOP interrupt disabled
1: STOP interrupt enabled
Bit 3 = GO Go.
This bit is set by ST7 software and cleared by
hardware. It is always read as ’0’. It generates a
pulse to launch the MSCI after it has been self-
stopped by an internal STOP instruction.
0: No effect
1: Generate a starting pulse
Bit 2 = RAMLD RAM Load.
This bit is set and cleared by ST7 software. The
MSCI must be under PC or Soft reset before start-
ing a read or write sequence. It can be written only
when PCR or SFTR is set (or when MSCI is
stopped by emulator in emulation mode)
See Section 14.2.4 and Section 14.2.4.1
0: RAM access from ST7 disabled
1: RAM access from ST7 enabled
Bit 1 = PCR Program Counter Reset.
This bit is set and cleared by ST7 software. It can
be written only when RAMLD is cleared.
0: MSCI program counter reset not forced
1: MSCI program counter forced to MPCM &
MPCL value.
Bit 0 = SFTR Soft Reset.
This bit is set and cleared by ST7 software. It can
be written only when RAMLD is cleared.
0: MSCI system reset not forced
1: MSCI system under reset.
MSCI STATUS REGISTER (MSR)
Read / Write
Reset Value: 0000 0000 (00h)
Bit 7:6 = Reserved
Bit 5 = ITR MSCI CORE ITR flag.
This bit is set by MSCI software and cleared by a
PC reset or a soft reset or by writing a ’1’ in the
CITR bit in ST7 software.
0: MSCI ITR flag not set
1: MSCI ITR flag set by an internal ITR instruction.
Bit 4 = STP MSCI CORE Stop flag.
This bit is set by MSCI software and cleared by a
PC reset or a soft reset or by writing a ’1’ in the
CSTP bit in ST7 software
0: MSCI stop flag not set
1: MSCI stop flag set by an internal STOP instruc-
tion
Bit 3:2 = Reserved
Bit 1 = CITR Clear ITR flag.
This bit is set by ST7 software to clear the MSCI
ITR flag and interrupt and reset by hardware. It is
always read as ’0’.
0: No effect
1: Clears MSCI ITR flag and interrupt if pending
Bit 0 = CSTP Clear Stop flag.
This bit is set by ST7 software to clear the MSCI
STOP flag and interrupt and reset by hardware. It
is always read as ’0’.
0: No effect
1: Clears MSCI STOP flag and interrupt if pending
Note:
To set the RAMLD bit when PCR=0 and SFTR=0,
two write accesses to MCR register are needed.
The first access must set either the SFTR bit or the
PCR bit to enable write access to RAMLD bit. The
second write access can set the RAMLD bit. Ex-
cept in emulation mode when MSCI is stopped by
emulator.
To clear the PCR bit or the SFTR bit when RAMLD
bit is set, two write accesses to MCR register are
needed. The first access to reset the RAMLD bit.
The second write access to clear PCR bit or SFTR
bit. This must be done also in emulation mode.
70
-
ITRIE
STPIE
GO
RAMLD PCR
SFTR
70
-
ITR
STP
-
CITR
CSTP
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