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参数资料
| 型号： | ST7267C8T1/XXX |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, MROM, 30 MHz, RISC MICROCONTROLLER, PQFP48 |
| 封装： | 7 X 7 MM, LEAD FREE, TQFP-48 |
| 文件页数： | 64/189页 |
| 文件大小： | 1643K |
| 代理商： | ST7267C8T1/XXX |
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ST7267C8 ST7267R8
156/189
MSCI PARALLEL INTERFACE (Cont’d)
PARALLEL INTERFACE CONFIGURATION REGISTER 2 (PCR2)
Read / Write
Reset Value: 0000 0000 0000 0000 (0000h)
Bit 15 = Reserved.
Bit 14 = ED ECC Disable.
This bit is set and cleared by software.
It disables the ECC generator and forces the ECC
line and column parities to reset value.
0: ECC generator enabled.
1: ECC generator disabled.
Bit 13 = RF Reset FIFO.(write only)
This bit is set by software and is always read as 0.
Writing ’1’ in this bit resets the FIFO to empty.
Note: this Reset FIFO command does not modify
the value of the number of bytes written in the
FIFO. The LBF byte will still rise after writing the
expected number of bytes in the FIFO even if
some were deleted by a FIFO reset. This bit must
be used only to force the FIFO to empty if the FIFO
is left at a non empty state at the end of a transfer.
Bit 12 = PID Parallel Interface Disable.
This bit is set and cleared by software.
Disabling the Parallel interface stops the commu-
nication and the double buffer but does not reset
the configuration registers.
Note: setting the PID bit does not release the con-
trol signal output enable and does not reset the
FIFO.
Important note: A reset in the MCSI software of
the PID bit and the setting of the START bit (of the
PCR1 register) must be separated by a delay of at
least 3 cycles. The use of 3 additional single-cycle
instructions following the reset can be used for this
purpose.
0: Parallel interface is enabled
1: Parallel interface is disabled
Bit 11:4 = CSE[7:0] Control Signal Enable.
These bits are set and cleared by software.
0: Control line output disabled
(not driven by control signal generator)
1: Control line output enabled
(driven by control signal generator)
Bit 3 = ROE Read On Edge.
This bit is set and cleared by software.
This bit is only used in input mode to define when
the input data has to be read. Read on edge con-
figuration must be selected for external devices
using Read enable signals. Read at end of cycle
configuration must be chosen for synchronous ex-
ternal devices with data maintained on data port.
0: Read at the end of each cycle.
1: Read on the active edge of the control signal.
Bit 2 = ESB ECC Swap Bytes.
This bit is set and cleared by software.
It selects the order of the bytes in the word when
sent to the ECC generator in 16-bit mode.
0: Do not swap bytes (most significant byte first)
1: Swap bytes (least significant byte first)
Bit 1 = FSB FIFO Swap Bytes.
This bit is set and cleared by software.
It selects the order of the bytes in the word when
reading/writing from/to the FIFO. It affects both
standard 16-bit access to FIFO and direct FIFO
copy with LDV instruction.
0: Do not swap bytes.
1: Swap bytes.
Bit 0 = CLDV Control Lines Default Value.
This bit is set and cleared by software.
It selects the default value that is forced on the ac-
tive control lines when no pulse is generated and
when communication is over or not started. When
the default value is changed, it will be effective on
the enabled control ports one 60 MHz clock cycle
after. To avoid an unexpected pulse on the control
signal, it is mandatory to change the CLDV value
only when all control lines are disabled.
0: Control line default value = 0
1: Control line default value = 1
Note: Configuration registers PNDR, PCR1 and
PCR2 must not be modified when a communi-
cation is on-going.
15
8
7
0
-
ED
RF
PID
CSE7
CSE6
CSE5
CSE4
CSE3
CSE2
CSE1
CSE0
ROE
ESB
FSB
CLDV
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