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ST7267C8 ST7267R8
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MSCI PARALLEL INTERFACE (Cont’d)
17.4 MSCI PARALLEL INTERFACE CONFIGURATION EXAMPLES
17.4.1 Examples for output mode
Once the parallel interface is configured and start-
ed, the communication begins as soon as one
communication buffer is full. If the double buffer is
filled by the MSCI software (through the FIFO)
faster than the data is sent to the I/Os, the commu-
nication will be continuous during the complete
packet. If the buffer becomes empty during a com-
munication, inactive states will be inserted to wait
until the buffer is ready. During these inactive
states, the data port is not driven by the parallel in-
terface, the control lines are frozen at the CLDV
level (Control Lines Default Value).
In output mode, data is always output at the begin-
ning of the control signal cycle whatever the con-
trol signal is. The control signal must be configured
in order to match targeted device protocol.
The Control Line Default Value (CLDV) parameter
is specific and must be configured before others
control signals parameter and before enabling any
Control Signal output with the CSE bits of the
PCR2 register.
Figure 61. Examples: output mode with F=010; CSS=010
Frequency=20MHz;
Duty Cycle=33%
waiting for Buffer
full again
control signal edge 2 periods after the
beginning of the control cycle
60MHz base period
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
CLDV=1
CP=1
CLDV=0
CP=1
CLDV=1
CP=0
CLDV=0
CP=0
Data output
Control signal port
DATA ports
Data ports selected (depending on the mode) controlled by parallel interface
data ports controlled
by MSCI I/O Controller
data ports controlled
by MSCI I/O Controlle
Note: In output mode, short spikes can be generated on data ports before data is stable (shorter.
than the data output delay).
.
Only the Control line signals are guaranteed to be spike free signals (mandatory for
synchronous communication).