![](http://datasheet.mmic.net.cn/140000/ST7267R8T1L-XXX_datasheet_5015361/ST7267R8T1L-XXX_146.png)
ST7267C8 ST7267R8
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MSCI PARALLEL INTERFACE (Cont’d)
17.4.2 Examples for input mode
Once the parallel interface configured and started,
the communication begins. If the double buffer is
read by the MSCI software (through the FIFO)
faster than the data is received from the I/Os, the
communication will be continuous during the com-
plete packet. If the two buffers become full during
a communication, inactive states will be inserted to
wait until the buffer is ready. During these inactive
states, the control lines are frozen at the CLDV
(Control Lines Default Value) level.
The data ports used are not forced to input mode
by the parallel interface. They must be configured
in input mode by the MSCI I/O controller (and by
the ST7 I/O Controller) to let an external device
drive them.
Figure 62. Examples: input mode with F=010; CSS=010; CP=1; CLDV=1
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
CLDV=1
CP=1
sync device
async device
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
CTRL signal port
DATA ports
data output
data sampling if ROE=1
data sampling if ROE=0
If the device is synchronous and outputs data after the falling
edge, the ROE can be reset to sample at the end of
the control signal cycle if setup time can be guaranteed.
If the device is asynchronous and data is output only when
control signal is low, the ROE bit must be set to sample
data on the rising edge of the control signal. (data output time
If setup time can not be guaranteed, then the ROE bit must
be set (data output time of the external device must
be shorter than the low level time on control line)
of the external device must be shorter than the low level time
on control line)
Note: If CP=0 configuration is selected (falling edge generated) only the control signal generation will be
modified. This means that data will be sampled on the falling edge of the control signal if ROE=1 or at
the end of the control signal if ROE=0.