- 您现在的位置：买卖IC网 > PDF目录98145 > ST7267C8T1/XXX (STMICROELECTRONICS) 16-BIT, MROM, 30 MHz, RISC MICROCONTROLLER, PQFP48 PDF资料下载
参数资料
| 型号： | ST7267C8T1/XXX |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, MROM, 30 MHz, RISC MICROCONTROLLER, PQFP48 |
| 封装： | 7 X 7 MM, LEAD FREE, TQFP-48 |
| 文件页数： | 5/189页 |
| 文件大小： | 1643K |
| 代理商： | ST7267C8T1/XXX |
第1页第2页第3页第4页当前第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页第148页第149页第150页第151页第152页第153页第154页第155页第156页第157页第158页第159页第160页第161页第162页第163页第164页第165页第166页第167页第168页第169页第170页第171页第172页第173页第174页第175页第176页第177页第178页第179页第180页第181页第182页第183页第184页第185页第186页第187页第188页第189页
ST7267C8 ST7267R8
102/189
tomatically cleared when a packet of OUTMAXP
bytes has been unloaded from the OUT FIFO.
When packets of less than the maximum packet
size are unloaded, OPR will have to be cleared
manually.
Bit 6 = Reserved.
Bit 4 = DMAE DMA Enable
0: DMA request for the OUT endpoint disabled
1: DMA request for the OUT endpoint enabled.
Bit 4 = DNY Disable Nyet
Software sets this bit to disable the sending of
NYET handshakes. When set, all successfully re-
ceived OUT packets are ACK’d including at the
point at which the FIFO becomes full.
Note: This bit only has effect in High-speed mode.
In this mode it should be set for all Interrupt end-
points.
Bit 3 = DMAM DMA Mode
Two modes of operation are supported: In DMA
Mode 0 a DMA request is generated for all re-
ceived packets, together with an interrupt (if ena-
bled); In DMA Mode 1 a DMA request (but no inter-
rupt) is generated for OUT packets of size OUT-
MAXP bytes and an interrupt (but no DMA re-
quest) is generated for OUT packets of any other
size. DMAM is set by software to select the DMA
mode.
0: DMA Mode 0
1: DMA Mode 1
Bit 2:0= Reserved.
OUT
CONTROL
STATUS
REGISTER
LSB
(OUTCSRL)
OUTCSRL is the LSB of a register that provides
control and status bits for OUT transactions
through the currently-selected endpoint.
Read/Write
Reset value: 0000 0000 (00h)
Bit 7 = CDT Clear Data Toggle.
Software writes a 1 to this bit to reset the endpoint
OUT data toggle to 0.
Bit 6 = STST Sent Stall
This bit is set when a STALL handshake is trans-
mitted. Software should clear this bit.
Bit 5= SDST Send Stall
Software writes a 1 to this bit to terminate the cur-
rent transaction. The STALL handshake will be
transmitted and then this bit will be cleared auto-
matically.
Bit 4= FLFI Flush FIFO (Self clearing)
Software writes a 1 to this bit to flush the next
packet to be read from the endpoint OUT FIFO.
Note: If the FIFO contains two packets, FlushFIFO
will need to be set twice to completely clear the
FIFO.
Bit 3:2 = Reserved.
Bit 1 = FIFU FIFO full flag
This bit is set when no more packets can be load-
ed into the OUT FIFO. FIFU is cleared by hard-
ware.
Bit 0 = OPR OUT Packet Ready flag
This bit is set when a data packet has been re-
ceived. Software should clear this bit when the
packet has been unloaded from the OUT FIFO. An
interrupt is generated (if enabled) when the bit is
set.
OUT COUNT REGISTER MSB (OUTCNTRM)
Read Only
Reset value: 0000 0000 (00h)
OUTCNTRM is the MSB register that holds the
number of received data bytes in the packet in the
OUT FIFO.
Note: The value returns changes as the contents
of the FIFO change and is only valid while OPR bit
in the OUTCSRL register is set.
70
CDT
STST
SDST
FLFI
0
FIFU
OPR
70
0
OC12
OC11
OC10
OC9
OC8
相关PDF资料 |
PDF描述 |
|---|---|
| ST72774S9T1/XXX | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP44 |
| ST72E734J6D0 | 8-BIT, UVPROM, 8 MHz, MICROCONTROLLER, CDIP42 |
| ST72T774S9T1 | 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PQFP44 |
| ST7294C6B6 | 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PDIP28 |
| ST72T94C6M6 | 8-BIT, OTPROM, MICROCONTROLLER, PDSO28 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ST72681/R12 | 制造商:STMicroelectronics 功能描述:CONTROLLER FOR HIGH-PERFORMANCE BUS-POWERED USB 2.0 FLASH DR - Trays |
| ST72681/S13 | 制造商:STMicroelectronics 功能描述:CONTROLLER FOR HIGH-PERFORMANCE - Trays |
| ST7271 | 制造商:Panasonic Industrial Company 功能描述:IC |
| ST7271N5B1-CLF | 制造商:STMicroelectronics 功能描述: |
| ST727X4-EMU2B | 制造商:STMicroelectronics 功能描述:REALTIME EMULATOR BOARD - Bulk |
发布紧急采购，3分钟左右您将得到回复。