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参数资料
| 型号： | ST7267C8T1/XXX |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, MROM, 30 MHz, RISC MICROCONTROLLER, PQFP48 |
| 封装： | 7 X 7 MM, LEAD FREE, TQFP-48 |
| 文件页数： | 33/189页 |
| 文件大小： | 1643K |
| 代理商： | ST7267C8T1/XXX |
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MSCI VCI INTERFACE (Cont’d)
Read / Write operation in normal mode
Normal mode means that the BM bit of the VCR is
reset: burst mode is not enabled.
To read a single word or byte message, once the
MSCI VCI Interface enabled and in idle state, the
MSCI CPU just has to read the word in the VFDR
(VCI FIFO Data Register).The MSCI CPU is
stopped until the data is available from the target
address.
The target address is given by the VTAR (VCI Tar-
get Address Register).
To write a single word or byte message, once the
MSCI VCI Interface in idle state, the MSCI CPU
just has to write the word to transmit in the VFDR
(VCI FIFO Data Register) if the FIFO is empty. The
word is automatically transmitted to the VCI Tar-
get.
Thus, from a software point of view, the FIFO reg-
ister acts like any other register in normal mode for
both Read and Write operations.
Note: after a write operation, the user has to wait
for the end of the communication by polling the CP
bit of the VSR before stopping the VCI interface
with the VCIEN bit of the VCR. If not, communica-
tion may be cut leading to an incorrect VCI mes-
sage transmission.
Read operation in burst mode
A complete message of N 8-Word packets can be
read from the register pointed to by VTAR (VCI
Target Address Register). The message size, N, is
defined by NP bits in the VCR (VCI Control Regis-
ter).
When the MSCI VCI Interface is on and in idle
state, the MSCI CPU reads the words in the VFDR
(VCI FIFO Data Register). Once the FIFO is emp-
ty, it is reloaded with the content of the VCI buffer
which contains the next packet. If the packet is not
available, the CPU is stopped until it arrives.
After the last word of the last packet has been
read, the LWR bit of the VSR (VCI Status Regis-
ter) is set.
Write operation in burst mode
A 8-Word packet can be written to the register
pointed to by VTAR (VCI Target Address Regis-
ter).
When the MSCI VCI Interface is on and in idle
state, the MSCI CPU writes the word to transmit in
the VFDR (VCI FIFO Data Register). Once the
FIFO is full (8 words have been written), its content
is automatically transmitted to the VCI buffer which
send on the VCI bus. The FIFO becomes empty
and the bit FE of the VCR (VCI Control Register) is
set, and thus, the CPU loads the next 8 words in
the FIFO.
Because of the FIFO structure, loads (LD instruc-
tion) must not be used with immediate value.
Note: after a write operation, the user has to wait
for the end of the communication by polling the CP
bit of the VSR before stopping the VCI interface
with the VCIEN bit of the VCR. If not, communica-
tion may be cut leading to an incorrect VCI mes-
sage transmission.
Both read or write can be performed through:
■
the regular MSCI bus: as in normal mode, the
FIFO register acts as a regular register.
■
the MSCI vectored bus: the complete FIFO is
read/write in one CPU cycle to/from an other
FIFO in the MSCI system. This is done using the
LDv instruction.
16.4 Error Management
The MSCI VCI Interface does not perform any er-
ror management.
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