ST7267C8 ST7267R8
148/189
MSCI PARALLEL INTERFACE (Cont’d)
17.6 ECC GENERATOR
The ECC generator is a hardware system that
computes Error Code Correction parity bits from
data sent or received by the parallel interface. It is
compliant with the Smart Media Card specifica-
tion. It allows correction of one bit in each 256-byte
data packet. It is designed to work with 512-byte
packets: two ECC codes are stored in internal reg-
isters and can be read by the MSCI core after the
512-byte packet has been sent or received by the
parallel interface.
Each Generated code is made of 16 line parity bits
and 6 column parity bits. This 22bit ECC is gener-
ated every 256 bytes of data. If the parallel inter-
face is used in 16-bit data mode, the data word is
split into two bytes that are sent to the ECC gener-
ator. The order of the bytes in the word for the
ECC generator can be selected with the bit 2 of the
PCR2 register (ECC Swap Bytes). For each 512-
byte packet, two ECC results are automatically
stored by the ECC generator without interrupting
the communication. The ECC generated for the
first 256 bytes is stored in the ELP1 and ECP1 reg-
isters, the ECC generated for the next 256 bytes is
stored in the ELP2 and ECP2 registers. If more
than 2*256 bytes are sent/received, only the two
first ECCs are stored. Two flags are available in
the PSR register to indicate whether ECC1 and
ECC2 are available for reading or not.
The ECC generator and the ECC line and column
parity registers are reset when a new start is per-
formed on the parallel interface.
Figure 65. ECC generator implementation
Word 7
Word 6
Word 5
Word 4
Word 3
Word 2
Word 1
Word 0
COM. BUFFER (0 or 1)
word/byte
conversion
ECC swap bytes
ECC generator
ELP1 register
ECP1 register
ELP2 register
ECP2 register
Input or Output
mode
ECC1 ready
ECC2 ready
previous data word
ECC1 stored
ECC2 stored
Status flags
received from I/Os