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参数资料
型号： ST72E85A5G0
厂商： STMICROELECTRONICS
元件分类： 微控制器/微处理器
英文描述： 8-BIT, UVPROM, 4.332 MHz, MICROCONTROLLER, CQFP80
封装： WINDOWED, CERAMIC, QFP- 80
文件页数： 28/117页
文件大小： 748K
代理商： ST72E85A5G0
18/117
ST7285C
3.3 RESETS
3.3.1 Introduction
There are four sources of Reset:
– RESET pin (external source)
– Power-On Reset (Internal source)
– WATCHDOG (Internal Source)
The Reset Service Routine vector is located at ad-
dress FFFEh-FFFFh.
3.3.2 External Reset
The RESET pin is both an input and an open-drain
output with integrated pull up resistor. When one
of the internal Reset sources is active, the Reset
pin is driven low to reset the whole application.
3.3.3 Reset Operation
The duration of the Reset condition, which is also
reflected on the output pin, is fixed at 4096 internal
CPU Clock cycles. A Reset signal originating from
an external source must have a duration of at least
1.5 internal CPU Clock cycles in order to be recog-
nised. At the end of the Power-On Reset cycle, the
MCU may be held in the Reset condition by an Ex-
ternal Reset signal. The RESET pin may thus be
used to ensure VDD has risen to a point where the
MCU can operate correctly before the User pro-
gram is run. Following a Reset event, or after exit-
ing Halt mode, a 4096 CPU Clock cycle delay pe-
riod is initiated in order to allow the oscillator to
stabilise and to ensure that recovery has taken
place from the Reset state.
During the Reset cycle, the device Reset pin acts
as an output that is pulsed low for 3 machine cy-
cles (6 oscillator cycles). In its high state, an inter-
nal pull-up resistor of about 300K
is connected to
the Reset pin. This resistor can be pulled low by
external circuitry to reset the device.
3.3.4 Power-on Reset
This circuit detects the ramping up of VDD,and
generates a pulse that is used to reset the applica-
tion (at approximately VDD= 2V).
Power-On Reset is designed exclusively to cope
with power-up conditions, and should not be used
in order to attempt to detect a drop in the power
supply voltage.
Caution:
to re-initialize the Power-On Reset, the
power supply must fall below approximately 0.8V
(Vtn), prior to rising above 2V. If this condition is
not respected, on subsequent power-up the Reset
pulse may not be generated. An external pulse
may be required to correctly reactivate the circuit.
Figure 9. Reset Block Diagram
VDD
CO
UNT
E
R
RESET
to ST7
VR2062C
300K
WATCHDOG RESET
OR DLPSS
RESET
OSCILLATOR
SIGNAL
INTERNAL
RESET
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