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参数资料
| 型号： | ST72E85A5G0 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, UVPROM, 4.332 MHz, MICROCONTROLLER, CQFP80 |
| 封装： | WINDOWED, CERAMIC, QFP- 80 |
| 文件页数： | 72/117页 |
| 文件大小： | 748K |
| 代理商： | ST72E85A5G0 |
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ST7285C
I
2C BUS INTERFACE (Cont’d)
DATA REGISTER (DR)
Address: 002Eh
—
Read / Write
Reset Value: 00h
In transmitter mode, DR contains the next byte of
data which is to be applied to the shift register. The
byte transmission begins after the DR write by the
microcontroller.
In receiver mode, DR contains the last byte of data
received from the shift register. The next byte re-
ceipt begins after the DR read by the microcontrol-
ler.
OWN ADDRESS REGISTER 1 (OAR1)
Address: 002Ch
—
Read / Write
Reset Value: 00h
In 7-bit addressing, [ADD7..ADD1] are the ad-
dress of the peripheral.
In 10-bit addressing, [ADD7..ADD0] are the least
significant bits of the address of the peripheral.
OWN ADDRESS REGISTER 2 (OAR2)
Address: 002Dh
—
Read / Write
Reset Value: 00h
b7-3 = reserved.
b2-1 = [ADDE2..ADDE1] are the most significant
bits of the address of the peripheral in 10-bit ad-
dressing.
In 7-bit addressing, the first byte following the start
condition is the address byte. The least significant
bit is the data direction bit.
In 10-bit addressing, the first two bytes following a
start condition are the address bytes. The first sev-
en bits of the first byte are the combination
11110xx of which the last two bits are the two most
significant bits of the 10-bits addressing; the eighth
bit is the data direction bit. The second byte con-
tains the remaining 8 bits of the 10-bit address.
b0 = reserved.
Various combinations of read/write formats in 10-
bit addressing:
Master-transmitter/Slave-receiver
When a 10-bit address follows a start condition
(S), each Slave compares the first seven bits of
the first byte of the Slave address (11110xx) with
its own address and tests the eighth bit. If the
Slave finds a match, it generates an acknowledge
(A1) and it compares the eight bits of the second
byte (xxxxxxxx) with its own address. If the Slave
finds a match, it generates an acknowledge (A2).
The Slave will remain addressed until it receives a
stop condition or a repeated start condition fol-
lowed by a different Slave address.
Master-receiver/Slave-transmitter
The direction of the transfer is changed after the
second data direction bit. Up to the acknowledge
bit A2, the procedure is the same as the one de-
scribed for a Master-transmitter/Slave-receiver.
After a repeated start condition, the Slave remem-
bers that it was addressed before. Then it com-
pares the seven bits of the first byte (11110XX)
with its own address.
70
DR7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
70
ADD7
ADD6
ADD5
ADD4
ADD3
ADD2
ADD1
ADD0
70
-----
ADDE2
ADDE1
-
S
Slave_address
1st 7bits
0A1
Slave_Adress
2nd byte
A2
data
A
S
Slave_adress
1st 7bits
0A1
Slave_Adress
2nd byte
A2
data
Sr
Slave_adress
1st 7bits
1
A
data
A
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