收藏本站
参数资料
型号： ST72E85A5G0
厂商： STMICROELECTRONICS
元件分类： 微控制器/微处理器
英文描述： 8-BIT, UVPROM, 4.332 MHz, MICROCONTROLLER, CQFP80
封装： WINDOWED, CERAMIC, QFP- 80
文件页数： 77/117页
文件大小： 748K
代理商： ST72E85A5G0
62/117
ST7285C
I
2C BUS INTERFACE (Cont’d)
4.5.6.3 Slave Sending
The Slave waits for the microcontroller to write in
the Data Register. Then it receives data in the
Shift Register and sends it on the SDA line. When
the acknowledge bit is received, the BTF flag is set
and an interrupt is generated if ITE is set.
- Detection of a Stop or Start condition during a
byte transfer: the state machine is reset, the BERR
flag is set and an interrupt is generated.
- Detection of a Start condition after an acknowl-
edge time-slot: the state machine is reset and it
starts a new process. So, the flag ADSL is set and
an interrupt is generated if ITE is set.
- Detection of a Stop condition after an acknowl-
edge time-slot: the state machine is reset. Then
the flag SSTOP is set and an interrupt is generat-
ed if ITE is set.
4.5.6.4 Master mode
The interface operates in Master mode after gen-
erating a Start condition. So, the Start flag must be
set in the control register and the I2C bus must be
free (Busy bit at logic low level).
Once the Start condition is generated, the M/SL
and SB flags are set and an interrupt is generated
if ITE is set. The interface waits for the microcon-
troller to write the Slave address in the Data Reg-
ister by holding the SCL line low.
The address byte is then sent on the SDA line, an
acknowledge clock pulse is sent on the SCL line
and an interrupt is generated if ITE is set. The in-
terface waits for the MCU to write to the Control
Register by holding the SCL line low. If there is no
acknowledge, the AF flag is set and the Master
must write a Start or a Stop in the Control Register.
The state machine then enters a send or a receive
process, depending on the state of the Data Direc-
tion bit (least significant bit); an interrupt is gener-
ated if ITE is set.
If the Master loses control of bus arbitration, there
will be no acknowledge. The AF flag is set and the
Master must write a Start or a Stop in the control
register; the ARLO flag is set, the M/SL flag is
cleared and the process is reset. An interrupt is
generated if ITE is set.
4.5.6.5 Master Sending
The Master waits for the MCU to write in the Data
Register by holding the SCL line low. Then the
byte is received in the shift register and is sent on
the SDA line. The BTF flag is set and an interrupt
is generated if ITE is set.
- Detection of a Stop or of a Start condition during
a byte transfer: the BERR flag is set and an inter-
rupt is generated if ITE is set.
- The Stop bit is set in the Control Register: a Stop
condition is generated after the transfer of the cur-
rent byte, the M/SL flag is cleared and the state
machine is reset. Then an interrupt is generated if
ITE is set.
- The Start bit is set in the Control Register: the
state machine is reset and it starts a new process.
The SB flag is set and an interrupt is generated if
ITE is set.
- There is no acknowledge: the AF flag is set and
an interrupt is generated if ITE is set.
4.5.6.6 Master Receiving
The Master receives a byte from the SDA line into
the shift register and it sends it to the Data Regis-
ter. So, it generates an acknowledge bit if the ACK
bit is set and it generates an interrupt if ITE is set.
Then it waits for the microcontroller to read the
Data Register by holding SCL line low.
- A detection of a Stop or a Start condition during a
byte reception: the flag BERR is set and an inter-
rupt is generated if ITE is set.
- The Stop bit is set in the Control Register: a Stop
condition is generated after the transfer of the cur-
rent byte, the M/SL flag is cleared and the state
machine is reset. Then an interrupt is generated if
ITE is set.
- The Start bit is set in the Control Register: the
state machine is reset and starts a new process.
So, the flag SB is set and an interrupt is generated
if ITE is set.
相关PDF资料
PDF描述
ST72F321J9T7 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP44
ST72F321J7T3 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP44
ST72F321J7T1 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP44
ST72F321J9T5 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP44
ST72F324BJ6B6 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDIP42
相关代理商/技术参数
参数描述
ST72F260G1B5 功能描述:8位微控制器 -MCU Flask 4K SPI RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT
ST72F260G1M6 功能描述:8位微控制器 -MCU Flash 4K SPI/I2C/SCI RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT
ST72F260G1M6/TR 功能描述:8位微控制器 -MCU 8B MCU FLASH OR ROM MEMORY RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT
ST72F262G1B5 功能描述:8位微控制器 -MCU Flask 4K SPI RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT
ST72F262G1B6 功能描述:8位微控制器 -MCU 8B MCU RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT
发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

*型号 *数量 厂商 批号 封装
添加更多采购

我的联系方式

*
*
*