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参数资料
| 型号： | ST72E85A5G0 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, UVPROM, 4.332 MHz, MICROCONTROLLER, CQFP80 |
| 封装： | WINDOWED, CERAMIC, QFP- 80 |
| 文件页数： | 64/117页 |
| 文件大小： | 748K |
| 代理商： | ST72E85A5G0 |
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ST7285C
SERIAL PERIPHERAL INTERFACE(Cont’d)
4.4.7 Serial Peripheral Control Register (SPCR)
Address: see Memory Map
—
Read/Write
Reset Value: 0Xh
The Serial Peripheral Control Register bits are de-
fined as follows.
Bit-7 = SPIE
Serial Peripheral Interrupt Enable
When the Serial Peripheral Interrupts Enable bit is
set a processor interrupt can occur. This forces the
proper vector to be loaded into the program coun-
ter if the Serial Peripheral Status Register flag bit
(SPIF) and /or MODF are set. SPIE does not inhib-
it the setting of a status bit. The SPIE bit is cleared
on Reset.
Bit-6 = SPE
Serial Peripheral output Enalble
When the Serial Peripheral Output Enable Control
bit is set, all output drive is applied to the external
pins and the system is enabled. When the SPE bit
is set, it enables the SPI system by connecting it to
the external pins thus allowing it to interface with
the external SPI bus. The pins that are defined as
outputs depend on which mode (Master or Slave)
the device is in. Because the SPE bit is cleared on
Reset, the SPI system is not connected to the ex-
ternal pins on Reset.
Bit-4 = MSTR Master
The Master bit determines whether the device is a
Master or a Slave. If the MSTR bit is reset it indi-
cates a Slave device, whent it is set it indicates a
Master device. If the Master mode is selected, the
function of the SCK pin changes from an input to
an output and the function of the MISO and MOSI
pins are reversed. This allows the user to wire de-
vice pins MISO to MOSI, and MOSI to MOSI, and
SCK to SCK without incident. The MSTR bit is
cleared on Reset: thus the device is always set in
Slave mode during Reset.
Bit-3 = CPOL
Clock POLarity
The Clock POLarity bit controls the normal or
steady state value of the clock when no data is be-
ing transferred. The CPOL bit affects both the
Master and Slave modes. It must be used in con-
junction with the Clock PHAse control bit (CPHA)
to produce the wanted clock-data relationship be-
tween a Master and a Slave device. When the
CP0L bit is reset, it produces a steady-state logic
low value on the SCK pin of the Master device. If
the CPOL bit is set, a logic high level is present on
the SCK pin of the Master device when data is not
being transferred. The CPOL bit is not affected by
Reset.
Bit-2 = CPHA Clock PHAse
The Clock PHAse bit controls the relationship be-
tween the data on the MISO and MOSI pins and
the clock produced or received at the SCK pin.
This control has effect in both the Master or Slave
modes. It must be used in conjunction with the
Clock Polarity control bit (CPOL) to produce the
wanted clock-data relationship. In general the
CPHA bit selects the clock edge which captures
data and allows it to change states. It has its great-
est impact on the first bit transmitted (MSB) in that
it does or does not allow a clock transition before
the first data capture edge. The CPHA bit is not af-
fected by Reset.
Bit-1 = SPR1 Serial Peripheral Rate bit 1
Bit-0 = SPR0 Serial Peripheral Rate bit 0
These two Serial Peripheral Rate bits select one of
four baud rates to be used for SCK when the de-
vice is a Master. However, these two bits have no
effect in Slave mode. The Slave device is capable
of shifting data in and out at a maximum rate which
is equal to the CPU clock. A rate table is given be-
low for SCK in Master mode. The SPR1 and SPR0
bits are not affected by Reset.
70
SPIE
SPE
-
MSTR
CPOL
CPHA
SPR1
SPR0
SPR1
SPR0
Internal Processor
Clock Division factor
00
2
01
4
10
16
11
32
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