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参数资料
型号： ST72E85A5G0
厂商： STMICROELECTRONICS
元件分类： 微控制器/微处理器
英文描述： 8-BIT, UVPROM, 4.332 MHz, MICROCONTROLLER, CQFP80
封装： WINDOWED, CERAMIC, QFP- 80
文件页数： 57/117页
文件大小： 748K
代理商： ST72E85A5G0
44/117
ST7285C
16-BIT TIMER (Cont’d)
TIMER STATUS REGISTER (TSR)
Address: see Memory Map
—
Read Only
Reset Value: 0000 0000b
The Timer Status Register (TSR) is an 8-bit regis-
ter of which the five most significant bits contain
read-only status information and the three least
significant bits are not used.
Bit 7 = ICF1 Input Capture Flag 1
ICF1 is set when a proper edge has been sensed
by the input capture edge detector at pin ICAP1.
The edge is selected by the IEDG1-bit in TCR.
ICF1 is cleared by a processor access to the TSR
while ICF1 is set followed by an access (read or
write) to the low byte of ICR1 (ICLR1).
Bit 6 = OCF1
Output Compare Flag 1
OCF1 is set when the content of the free running
counter matches the content of OCR1. It is cleared
by a processor access of TSR while OCF1 is set
followed by an access (read or write) to the low
byte of OCR1.
Bit 5 = TOF
Timer Overflow
TOF is set by a transition of the free running coun-
ter from FFFFh to 0000h. It is cleared by a proces-
sor access to TSR while TOF is set followed by an
access (read or write) to the low byte of the coun-
ter low register. TOF is not affected by an access
to the Alternate Counter Register.
Bit 4 = ICF2 Input Capture Flag 2
ICF2 is set when a proper edge has been sensed
by the input capture edge detector at pin ICAP2.
The edge is selected by the IEDG2-bit in TCR.
ICF2 is cleared by a processor access to the TSR
while ICF2 is set followed by an access (read or
write) to the low byte of ICR2 (ICLR2).
Bit 3 = OCF2
Output Compare Flag 2
OCF2 is set when the content of the free running
counter matches the content of OCR2. It is cleared
by a processor access of TSR while OCF2 is set
followed by an access (read or write) to the low
byte of OCR2.
Bit 2, 1, 0 = Unused.
70
ICF1
OCF1
TOF
ICF2
OCF2
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