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| 型号： | ST72E85A5G0 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, UVPROM, 4.332 MHz, MICROCONTROLLER, CQFP80 |
| 封装： | WINDOWED, CERAMIC, QFP- 80 |
| 文件页数： | 84/117页 |
| 文件大小： | 748K |
| 代理商： | ST72E85A5G0 |
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ST7285C
RDS DEMODULATOR (Cont’d)
4.8.2 Functional Description
The RDS Demodulator is fed with a 57KHz band-
pass filtered and limited multiplex signal.
It contains the following functional blocks:
– 57kHz PLL. This circuit is implemented as a var-
iable counter controlled by a “COSTAS” phase
comparator. To achieve fast lockup time, the low-
pass filter features four software selectable time
constants. Following a reset, the longest time
constant is selected and used for the locked con-
dition. The time constant relates to the time
needed to compensate a 90 degree phase devi-
ation. As the PLL locks to 0 and 180 degrees,
whatever is closest, this is the maximum possible
phase deviation. The selectable time constants
are listed in the following register description.
– 1187.5Hz PLL. This circuit detects zero cross-
ings of the phase of the input signal. After low
pass filtering, this information is used to control a
variable divider, which generates the RDS clock.
The time constant of the low pass filter is also se-
lectable in four steps.
The regulation of both PLLs may be inhibited by
software. This may be used to “freeze” the actual
phase relation in order to bridge a certain time of
weak or non-existing input signal. (e.g. during AF
tests, breakdown in field strength,...). Depending
of the precision of the quartz oscillator some sec-
onds of weak input signal may be spanned with-
out loosing the lock condition.
– “Polarity” Phase Decoder. With the help o the
recovered 57kHz carrier, the sign of the input sig-
nal phase is integrated over one bit (48 sam-
ples).
– “Integral” Phase Decoder. The relative phase
angle of the input signal to the recovered carrier
is measured. Again 48 samples are accumulat-
ed. Regarding of the “polarity phase decoder,
this system is less sensitive to the precision of
the recovered carrier, but is more sensitive with
respect to ignition spikes.
– Differential Decoder. Every phase decoder out-
put is fed into its own differential decoder. For er-
ror correction purposes, a quality bit can be
generated in order to mark all differences be-
tween the two decoder outputs.
– Quality Detector. This unit measures the amount
of opposite phase samples. With an error free sig-
nal; every bit consists of 24 positive and 24 neg-
ative phase samples related to the carrier. Due to
noise, this balance may be disturbed. all bits with
a relation greater than 40 to 8 are marked as bad.
This quality information may be used by the soft-
ware for an improved error correction. It also may
be used internally (selection by software) to
switch automatically between “polarity” and “inte-
gral” phase decoders.
The source of RDS data may be one or the other
output of these two decoders.
The source of the quality output may be selected
from the quality detector or from the exor which
builds the difference between the two differential
decoders.
– ARI Indicator. In order to receive a correct RDS
signal, the57KHz PLL regulation mustbe changed
in accordance with the presence of ARI. Therefore
a fast ARI indicator is implemented. This function
may be optionally taken over by software.
– Interface Registers. These allow control of the
Demodulator circuit by the MCU. Register de-
scriptions are given below:
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