Electrical Specifications
144
March 2004 Revised October 2004
SGUS051A
Table 645. McBSP Switching Characteristics
NO.
PARAMETER
MIN
MAX
UNIT
M1
tc(CKRX)
tw(CKRXH)
tw(CKRXL)
Cycle time, CLKR/X
CLKR/X int
2P
ns
M2
Pulse duration, CLKR/X high
CLKR/X int
D5§
C5§
D+5§
C+5§
ns
M3
Pulse duration, CLKR/X low
CLKR/X int
ns
M4
td(CKRH-FRV)
Delay time, CLKR high to internal FSR valid
CLKR int
0
4
ns
CLKR ext
3
27
ns
M5
td(CKXH-FXV)
Delay time, CLKX high to internal FSX valid
CLKX int
0
4
ns
CLKX ext
3
27
M6
tdis(CKXH-DXHZ)
Disable time, CLKX high to DX high impedance
following last data bit
CLKX int
8
ns
CLKX ext
14
Delay time, CLKX high to DX valid.
This applies to all bits except the first bit transmitted.
CLKX int
9
CLKX ext
28
M7
td(CKXH-DXV)
DXENA = 0
CLKX int
8
Delay time, CLKX high to DX valid
CLKX ext
14
ns
Only applies to first bit transmitted when in Data
Delay 1 or 2 (XDATDLY=01b or 10b) modes
DXENA = 1
CLKX int
P + 8
CLKX ext
P + 14
DXENA = 0
CLKX int
0
M8
ten(CKXH-DX)
Enable time, CLKX high to DX driven
CLKX ext
6
ns
Only applies to first bit transmitted when in Data
Delay 1 or 2 (XDATDLY=01b or 10b) modes
DXENA = 1
CLKX int
P
CLKX ext
P + 6
DXENA = 0
FSX int
8
M9
td(FXH-DXV)
Delay time, FSX high to DX valid
FSX ext
14
ns
Only applies to first bit transmitted when in Data
Delay 0 (XDATDLY=00b) mode.
DXENA = 1
FSX int
P + 8
FSX ext
P + 14
DXENA = 0
FSX int
0
M10
ten(FXH-DX)
Enable time, FSX high to DX driven
FSX ext
6
ns
Only applies to first bit transmitted when in Data
Delay 0 (XDATDLY=00b) mode
DXENA = 1
FSX int
P
FSX ext
P + 6
Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of
that signal are
also inverted.
2P = 1/CLKG in ns.
§C=CLKRX low pulse width = P
D=CLKRX high pulse width = P