参数资料
型号: TMX20F2810PBKAEP
厂商: Texas Instruments, Inc.
元件分类: 数字信号处理
英文描述: Digital Signal Processors
中文描述: 数字信号处理器
文件页数: 148/159页
文件大小: 2084K
代理商: TMX20F2810PBKAEP
Electrical Specifications
146
March 2004 Revised October 2004
SGUS051A
6.31.2
McBSP as SPI Master or Slave Timing
Table 646. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
NO.
MASTER
SLAVE
UNIT
MIN
P10
MAX
MIN
8P10
MAX
M30
tsu(DRV-CKXL)
th(CKXL-DRV)
tsu(BFXL-CKXH)
tc(CKX)
Setup time, DR valid before CLKX low
ns
M31
Hold time, DR valid after CLKX low
P10
8P10
ns
M32
Setup time, FSX low before CLKX high
8P+10
ns
M33
Cycle time, CLKX
2P
16P
ns
Table 647. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
NO.
PARAMETER
MASTER
SLAVE
UNIT
MIN
MAX
MIN
MAX
M24
th(CKXL-FXL)
td(FXL-CKXH)
Hold time, FSX low after CLKX low
2P
ns
M25
Delay time, FSX low to CLKX high
P
ns
M28
tdis(FXH-DXHZ)
Disable time, DX high impedance following
last data bit from FSX high
6
6P + 6
ns
M29
td(FXL-DXV)
Delay time, FSX low to DX valid
6
4P + 6
ns
2P = 1/CLKG
For all SPI slave modes, CLKX has to be minimum 8 CLKG cycles. Also CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1. With
maximum LSPCLK speed of 75 MHz, CLKX maximum frequency will be LSPCLK/16 , that is 4.5 MHz and P =13.3 ns.
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
CLKX
FSX
DX
M30
M31
DR
M28
M24
M29
M25
LSB
MSB
M32
M33
Figure 643. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
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