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参数资料
| 型号： | WJLXT388LEB2 |
| 厂商： | CORTINA SYSTEMS INC |
| 元件分类： | 数字传输电路 |
| 英文描述： | DATACOM, PCM TRANSCEIVER, PQFP100 |
| 封装： | 14 X 14MM, ROHS COMPLIANT, LQFP-100 |
| 文件页数： | 11/80页 |
| 文件大小： | 1017K |
| 代理商： | WJLXT388LEB2 |
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Dual T1/E1/J1 Transceiver — Intel
LXT388
Datasheet
19
90
91
92
93
94
95
96
97
D0/LOOP0
D1/LOOP1
D2/LOOP2
D3/LOOP3
D4/DLOOP0
D5/DLOOP1
D6/DLOOP2
D7/DLOOP3
DI/O
Loopback Mode Select/Parallel Data bus.
Host Mode:
When a non-multiplexed microprocessor interface is selected, these pins function as a bi-
directional 8-bit data port.
When a multiplexed microprocessor interface is selected, these pins carry both bi-
directional 8-bit data and address inputs A0 -A7.
In serial Mode, D0-7 should be grounded.
Hardware Mode:
In hardware mode, these pins control the operation of transceivers 0, 1 and receivers 2, 3
according to the table below.
During remote loopback mode, data on TPOS and TNEG is ignored and data received on
RTIP and RRING is looped around and retransmitted on TTIP and TRING. Note: in data
recovery mode, the pulse template cannot be guaranteed while in a remote loopback.
In analog local loopback mode, data received on RTIP and RRING is ignored and data
transmitted on TTIP and TRING is internally looped around and routed back to the
receiver inputs.
In digital local loopback mode, data received on TCLK/TPOS/TNEG is digitally looped
back to RCLK/RPOS/RNEG.
Note: When these inputs are left open, they stay in a high impedance state. Therefore,
the layout design should not route signals with fast transitions near the LOOP pins. This
practice will minimize capacitive coupling.
99
MUX
DI
Multiplexed/Non-Multiplexed Select.
When Low the parallel host interface operates in non-multiplexed mode. When High the
parallel host interface operates in multiplexed mode. In hardware mode tie this unused
input low.
98
CS/
JASEL
DI
Chip Select/Jitter Attenuator Select.
Host Mode
This active Low input is used to access the serial/parallel interface. For each read or write
operation, CS must transition from High to Low, and remain Low.
Hardware Mode
This input determines the Jitter Attenuator position in the data path.
Table 5.
Pin Assignments and Signal Descriptions - Microprocessor/Configuration
Pin #
LQFP
Symbol
I/O
1
Description
1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply;
N.C.: Not Connected.
LOOP
DLOOP
Operating Mode
Transceivers 0,1
Operating Mode
Receivers 2, 3
Open
x
Normal Mode
0
x
Remote Loopback
-
1
0
Analog Local Loopback
-
1
Digital Local Loopback
JASEL
JA Position
L
Transmit path
H
Receive path
Z
Disabled
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