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参数资料
| 型号： | WJLXT388LEB2 |
| 厂商： | CORTINA SYSTEMS INC |
| 元件分类： | 数字传输电路 |
| 英文描述： | DATACOM, PCM TRANSCEIVER, PQFP100 |
| 封装： | 14 X 14MM, ROHS COMPLIANT, LQFP-100 |
| 文件页数： | 9/80页 |
| 文件大小： | 1017K |
| 代理商： | WJLXT388LEB2 |
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Dual T1/E1/J1 Transceiver — Intel
LXT388
Datasheet
17
81
ACK/
RDY/
SDO
DO
Data Transfer acknowledge (Motorola Mode).
Ready (Intel mode).
Serial Data Output (Serial Mode).
Motorola Mode
A Low signal during a databus read operation indicates that the information is valid. A
Low signal during a write operation acknowledges that a data transfer into the addressed
register has been accepted (acknowledge signal).Wait states only occur if a write cycle
immediately follows a previous read or write cycle (e.g. read modify write).
Intel Mode
A High signal acknowledges that a register access operation has been completed (Ready
Signal). A Low signal on this pin signals that a data transfer operation is in progress. The
pin goes tristate after completion of a bus cycle.
Serial Mode
If CLKE is High, SDO is valid on the rising edge of SCLK. If CLKE is Low, SDO is valid on
the falling edge of SCLK. This pin goes into high Z state during a serial port write access.
82
ALE/
SCLK/
AS/
LEN2
DI
Address Latch Enable (Host Mode).
Shift Clock (Serial Mode).
Address Strobe (Motorola Mode).
Line Length Equalizer (Hardware Mode).
Host Mode
The address on the multiplexed address/data bus is clocked into the device with the
falling edge of ALE.
In serial Host mode this pin acts as serial shift clock.
In Motorola mode this pin acts a an active Low address strobe.
Hardware Mode
This pin determines the shape and amplitude of the transmit pulse in transceivers 0 and
1. It also determines the receiver setting (T1 or E1) in all the receivers. Please refer to
83
OE
DI
Output Driver Enable. If this pin is asserted Low all analog driver outputs immediately
enter a high impedance mode to support redundancy applications without external
mechanical relays. All other internal circuitry stays active. In software mode, TTIP and
TRING can be tristated on a port-by-port basis by writing a ‘1’ to the OEx bit in the Output
Enable Register (OER).
84
CLKE
DI
Clock Edge Select. In clock recovery mode, setting CLKE High causes RDATA or RPOS
and RNEG to be valid on the falling edge of RCLK and SDO to be valid on the rising edge
of SCLK. Setting CLKE Low makes RDATA or RPOS and RNEG to be valid on the rising
edge of RCLK and SDO to be valid on the falling edge of SCLK. In Data recovery Mode,
RDATA or RPOS/RNEG are active High output polarity when CLKE is High and active low
polarity when CLKE is Low.
Table 5.
Pin Assignments and Signal Descriptions - Microprocessor/Configuration
Pin #
LQFP
Symbol
I/O
1
Description
1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply;
N.C.: Not Connected.
CLKE
RPOS/RNEG
SDO
Low
High
SCLK
RCLK
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