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参数资料
| 型号： | WJLXT388LEB2 |
| 厂商： | CORTINA SYSTEMS INC |
| 元件分类： | 数字传输电路 |
| 英文描述： | DATACOM, PCM TRANSCEIVER, PQFP100 |
| 封装： | 14 X 14MM, ROHS COMPLIANT, LQFP-100 |
| 文件页数： | 6/80页 |
| 文件大小： | 1017K |
| 代理商： | WJLXT388LEB2 |
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Intel
LXT388 — Dual T1/E1/J1 Transceiver
14
Datasheet
63
TPOS2/
TDATA2
DI
Transmit Positive Data.
Transmit Data.
64
TCLK2
DI
Transmit Clock.
78
MCLK
DI
Master Clock. MCLK is an independent, free-running reference clock. It’s frequency
should be 1.544 MHz for T1 operation and 2.048 MHz for E1 operation.
This reference clock is used to generate several internal reference signals:
Timing reference for the integrated clock recovery unit
Timing reference for the integrated digital jitter attenuator
Generation of RCLK signal during a loss of signal condition
Reference clock during a blue alarm transmit all ones condition
Reference timing for the parallel processor wait state generation logic
If MCLK is High, the PLL clock recovery circuit is disabled. In this mode, the LXT388
operates as simple data receiver.
If MCLK is Low, the complete receive path is powered down and the output pins RCLK,
RPOS and RNEG are switched to Tri-state mode.
MCLK is not required if LXT388 is used as a simple analog front-end without clock
recovery and jitter attenuation.
Note that wait state generation via RDY/ACK is not available if MCLK is not provided.
100
RESET
DI
Reset Input. (Added in Revision B1) In either hardware mode or software mode, setting
RESET low will begin to initialize the LXT388 and freeze the device until set high. One
microsecond after setting RESET high, initialization will complete and the LXT388 will be
ready for normal operation. Only revision B1 requires a pull up resistor to VCC at this pin
between 1 and 10 kohms in value. It is necessary to retain the pull up resistor for other
revisions. Please refer to the section on Reset Operation for more information.
Table 3.
Pin Assignments and Signal Descriptions - Analog Interface
Pin #
LQFP
Symbol
I/O
1
Description
27
28
TTIP0
TRING0
AO
Transmit Tip.
Transmit Ring.
These pins are differential line driver outputs. TTIP and TRING will be in high impedance
state if the TCLK pin is Low or the OE pin is Low. In software mode, TTIP and TRING can
be tristated on a port-by-port basis by writing a ‘1’ to the OEx bit in the Output Enable
Register (OER).
30
31
RTIP0
RRING0
AI
Receive Tip.
Receive Ring.
These pins are the inputs to the differential line receiver. Data and clock are recovered
and output on the RPOS/RNEG and RCLK pins.
33
34
TRING1
TTIP1
AO
Transmit Ring.
Transmit Tip.
1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply;
N.C.: Not Connected.
Table 2.
Pin Assignments and Signal Descriptions - Digital Interface (Continued)
Pin #
LQFP
Symbol
I/O
1
Description
1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply;
N.C.: Not Connected.
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