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| 型号： | WJLXT388LEB2 |
| 厂商： | CORTINA SYSTEMS INC |
| 元件分类： | 数字传输电路 |
| 英文描述： | DATACOM, PCM TRANSCEIVER, PQFP100 |
| 封装： | 14 X 14MM, ROHS COMPLIANT, LQFP-100 |
| 文件页数： | 31/80页 |
| 文件大小： | 1017K |
| 代理商： | WJLXT388LEB2 |
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Dual T1/E1/J1 Transceiver — Intel
LXT388
Datasheet
37
2.12.2
Intel Interface
The Intel interface is selected by asserting the MOT/INTL pin High. The LXT388 supports non-
multiplexed interfaces with separate address and data pins when MUX is asserted Low, and
multiplexed interfaces when MUX is asserted High. The address is latched in on the falling edge of
ALE. In non-multiplexed mode, ALE should be pulled High. R/W is used as the RD signal and DS
is used as the WR signal. A read cycle is indicated to the LXT388 when the processor asserts RD
Low while the WR signal is held High. A write operation is indicated to the LXT388 by asserting
WR Low while the RD signal is held High. Both cycles require the CS signal to be Low.
2.13
Interrupt Handling
2.13.1
Interrupt Sources
There are three interrupt sources:
1. Status change in the Loss Of Signal (LOS) status register (04H). The LXT388’s analog/digital
loss of signal processor continuously monitors the receiver signal and updates the specific
LOS status bit to indicate presence or absence of a LOS condition.
2. Status change in the Driver Failure Monitoring (DFM) status register (05H). The LXT388’s
smart power driver circuit continuously monitors the output drivers signal and updates the
specific DFM status bit to indicate presence or absence of a secondary driver short circuit
condition.
3. Status change in the Alarm Indication Signal (AIS) status register (13H).The LXT388’s
receiver monitors the incoming data stream and updates the specific AIS status bit to indicate
presence or absence of a AIS condition.
2.13.2
Interrupt Enable
The LXT388 provides a latched interrupt output (INT). An interrupt occurs any time there is a
transition on any enabled bit in the status register. Registers 06H, 07H and 14H are the LOS, DFM
and AIS interrupt enable registers (respectively). Writing a logic “1” into the mask register will
enable the respective bit in the respective Interrupt status register to generate an interrupt. The
power-on default value is all zeroes. The setting of the interrupt enable bit does not affect the
operation of the status registers.
Registers 08H, 09H and 15H are the LOS, DFM and AIS (respectively) interrupt status registers.
When there is a transition on any enabled bit in a status register, the associated bit of the interrupt
status register is set and an interrupt is generated (if one is not already pending). When an interrupt
occurs, the INT pin is asserted Low. The output stage of the INT pin consists only of a pull-down
device; an external pull-up resistor of approximately 10k ohm is required to support wired-OR
operation.
2.13.3
Interrupt Clear
When an interrupt occurs, the interrupt service routine (ISR) should read the interrupt status
registers (08H, 09H and 15H) to identify the interrupt source. Reading the Interrupt Status register
clears the "sticky" bit set by the interrupt. Automatically clearing the register prepares it for the
next interrupt. The ISR should then read the corresponding status monitor register to obtain the
current status of the device. Note: there are three status monitor registers: the LOS (04H), the DFM
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