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参数资料
| 型号： | WJLXT388LEB2 |
| 厂商： | CORTINA SYSTEMS INC |
| 元件分类： | 数字传输电路 |
| 英文描述： | DATACOM, PCM TRANSCEIVER, PQFP100 |
| 封装： | 14 X 14MM, ROHS COMPLIANT, LQFP-100 |
| 文件页数： | 8/80页 |
| 文件大小： | 1017K |
| 代理商： | WJLXT388LEB2 |
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Intel
LXT388 — Dual T1/E1/J1 Transceiver
16
Datasheet
Table 5.
Pin Assignments and Signal Descriptions - Microprocessor/Configuration
Pin #
LQFP
Symbol
I/O
1
Description
1
MOT/INTL/
CODEN
DI
Motorola/Intel/Codec Enable Select.
Host Mode:
When Low, the host interface is configured for Motorola microcontrollers. When High, the
host interface is configured for Intel microcontrollers.
Hardware Mode:
This pin determines the line encode/decode selection when in unipolar mode:
When Low, B8ZS/HDB3 encoders/decoders are enabled for T1/E1 respectively. When
High, enables AMI encoder/decoder (transparent mode).
2
R / W/
RD/
LEN1
DI
Read/Write (Motorola Mode).
Read Enable (Intel mode).
Line Length Equalizer (Hardware Mode).
Host Mode
This pin functions as the read/write signal in Motorola mode and as the Read Enable in
Intel mode.
Hardware Mode
This pin determines the shape and amplitude of the transmit pulse. Refer to Table 6.
3
DS/
WR/
SDI/
LEN0
DI
Data Strobe (Motorola Mode).
Write Enable (Intel mode).
Serial Data Input (Serial Mode).
Line Length Equalizer (Hardware Mode).
Host Mode
This pin acts as data strobe in Motorola mode and as Write Enable in Intel mode. In serial
mode this pin is used as Serial Data Input.
Hardware Mode
This pin determines the shape and amplitude of the transmit pulse. Refer to Table 6.
79
MODE
DI
Mode Select. This pin is used to select the operating mode of the LXT386. In Hardware
Mode, the parallel processor interface is disabled and hardwired pins are used to control
configuration and report status.
In Parallel Host Mode, the parallel port interface pins are used to control configuration and
report status.
In Serial Host Mode the serial interface pins: SDI, SDO, SCLK and CS are used
For Serial Host Mode, the pin should connected to a resistive divider consisting of two 10
k
Ω resistors across VCC and Ground.
80
INT
DO
Interrupt. This active Low, maskable, open drain output requires an external 10k pull up
resistor. If the corresponding interrupt enable bit is enabled, INT goes Low to flag the host
when the LXT388 changes state (see details in the interrupt handling section). The
microprocessor INT input should be set to level triggering.
1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply;
N.C.: Not Connected.
MODE
Operating Mode
L
Hardware Mode
H
Parallel Host Mode
Vcc/2
Serial Host Mode
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